<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26793">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/haswell: Switch to POSTCAR_STAGE<br><br>Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/haswell/Makefile.inc<br>D src/cpu/intel/haswell/cache_as_ram.inc<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/haswell/romstage.c<br>M src/northbridge/intel/haswell/Kconfig<br>M src/northbridge/intel/haswell/Makefile.inc<br>6 files changed, 29 insertions(+), 382 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/26793/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc</span><br><span>index dc7170b..a0c892a 100644</span><br><span>--- a/src/cpu/intel/haswell/Makefile.inc</span><br><span>+++ b/src/cpu/intel/haswell/Makefile.inc</span><br><span>@@ -9,17 +9,14 @@</span><br><span> ramstage-y += monotonic_timer.c</span><br><span> </span><br><span> romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c</span><br><span> smm-y += monotonic_timer.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span> cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span> postcar-y += ../car/non-evict/exit_car.S</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span> </span><br><span> subdirs-y += ../../x86/tsc</span><br><span> subdirs-y += ../../x86/mtrr</span><br><span>diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc</span><br><span>deleted file mode 100644</span><br><span>index 388c2ea..0000000</span><br><span>--- a/src/cpu/intel/haswell/cache_as_ram.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,297 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/post_code.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* The full cache-as-ram size includes the cache-as-ram portion from coreboot</span><br><span style="color: hsl(0, 100%, 40%);">- * and the space used by the reference code. These 2 values combined should</span><br><span style="color: hsl(0, 100%, 40%);">- * be a power of 2 because the MTRR setup assumes that. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_SIZE \</span><br><span style="color: hsl(0, 100%, 40%);">- (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Cache 4GB - MRC_SIZE_KB for MRC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define NoEvictMod_MSR 0x2e0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the BIST result. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cache_as_ram:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x20)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Send INIT IPI to all excluding ourself. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x000C4500, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0xFEE00300, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, (%esi)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* All CPUs need to be in Wait for SIPI state */</span><br><span style="color: hsl(0, 100%, 40%);">-wait_for_sipi:</span><br><span style="color: hsl(0, 100%, 40%);">- movl (%esi), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- bt $12, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- jc wait_for_sipi</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x21)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Zero out all fixed range and variable range MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $mtrr_table, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $((mtrr_table_end - mtrr_table) >> 1), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">-clear_mtrrs:</span><br><span style="color: hsl(0, 100%, 40%);">- movw (%esi), %bx</span><br><span style="color: hsl(0, 100%, 40%);">- movzx %bx, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- add $2, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- dec %edi</span><br><span style="color: hsl(0, 100%, 40%);">- jnz clear_mtrrs</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x22)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Configure the default memory type to uncacheable. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~0x00000cff), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x23)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x24)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x25)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache (CR0.CD = 0, CR0.NW = 0). */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the 'no eviction' mode */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear the cache memory region. This will also fill up the cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CACHE_AS_RAM_BASE, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esi, %edi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- // movl $0x23322332, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- rep stosl</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the 'no eviction run' state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $3, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x26)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Cache-as-RAM mode by disabling cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache for our code in Flash because we do XIP here */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(0, 100%, 40%);">- * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $copy_and_run, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_TYPE_WRPROT, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x27)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable caching for RAM init code to run faster */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x28)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup the stack. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore the BIST result. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebp, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-before_romstage:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x29)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call romstage.c main function. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction run state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction mode */</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3a)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache again. */</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.Lhlt:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(0, 100%, 40%);">- hlt</span><br><span style="color: hsl(0, 100%, 40%);">- jmp .Lhlt</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fixed MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x250, 0x258, 0x259</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x268, 0x269, 0x26A</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26B, 0x26C, 0x26D</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26E, 0x26F</span><br><span style="color: hsl(0, 100%, 40%);">- /* Variable MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x200, 0x201, 0x202, 0x203</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x204, 0x205, 0x206, 0x207</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x208, 0x209, 0x20A, 0x20B</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x20C, 0x20D, 0x20E, 0x20F</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x210, 0x211, 0x212, 0x213</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table_end:</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 6612509..87c0909 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -180,10 +180,7 @@</span><br><span> * +32: MTRR mask 1 63:32</span><br><span> * ...</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *romstage_main(unsigned long bist);</span><br><span style="color: hsl(0, 100%, 40%);">-/* romstage_after_car() is the C function called after cache-as-ram has</span><br><span style="color: hsl(0, 100%, 40%);">- * been torn down. It is responsible for loading the ramstage. */</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void romstage_after_car(void);</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void romstage_main(unsigned long bist);</span><br><span> #endif</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span>diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c</span><br><span>index 6d9fbc4..ba26fb5 100644</span><br><span>--- a/src/cpu/intel/haswell/romstage.c</span><br><span>+++ b/src/cpu/intel/haswell/romstage.c</span><br><span>@@ -66,84 +66,39 @@</span><br><span> return stack;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* setup_romstage_stack_after_car() determines the stack to use after</span><br><span style="color: hsl(0, 100%, 40%);">- * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void *setup_romstage_stack_after_car(void)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* platform_enter_postcar() determines the stack to use after</span><br><span style="color: hsl(120, 100%, 40%);">+ * cache-as-ram is torn down as well as the MTRR settings to use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * and continues execution in postcar stage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static void platform_enter_postcar(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int num_mtrrs;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *slot;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 mtrr_mask_upper;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 top_of_ram;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct postcar_frame pcf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Top of stack needs to be aligned to a 4-byte boundary. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = (void *)romstage_ram_stack_top();</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The upper bits of the MTRR mask need to set according to the number</span><br><span style="color: hsl(0, 100%, 40%);">- * of physical address bits. */</span><br><span style="color: hsl(0, 100%, 40%);">- mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The order for each MTRR is value then base with upper 32-bits of</span><br><span style="color: hsl(0, 100%, 40%);">- * each value coming before the lower 32-bits. The reasoning for</span><br><span style="color: hsl(0, 100%, 40%);">- * this ordering is to create a stack layout like the following:</span><br><span style="color: hsl(0, 100%, 40%);">- * +0: Number of MTRRs</span><br><span style="color: hsl(0, 100%, 40%);">- * +4: MTRR base 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +8: MTRR base 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +12: MTRR mask 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +16: MTRR mask 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +20: MTRR base 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +24: MTRR base 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +28: MTRR mask 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +32: MTRR mask 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unable to initialize postcar frame.\n");</span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- top_of_ram = (uint32_t)cbmem_top();</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache 8MiB below the top of RAM. On haswell systems the top of</span><br><span style="color: hsl(0, 100%, 40%);">- * RAM under 4GiB is the start of the TSEG region. It is required to</span><br><span style="color: hsl(0, 100%, 40%);">- * be 8MiB aligned. Set this area as cacheable so it can be used later</span><br><span style="color: hsl(0, 100%, 40%);">- * for ramstage before setting up the entire RAM as cacheable. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB</span><br><span style="color: hsl(120, 100%, 40%);">+ * above top of the ram. This satisfies MTRR alignment requirement</span><br><span style="color: hsl(120, 100%, 40%);">+ * with different TSEG size configurations.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems</span><br><span style="color: hsl(0, 100%, 40%);">- * is where the TSEG region resides. However, it is not restricted</span><br><span style="color: hsl(0, 100%, 40%);">- * to SMM mode until SMM has been relocated. By setting the region</span><br><span style="color: hsl(0, 100%, 40%);">- * to cacheable it provides faster access when relocating the SMM</span><br><span style="color: hsl(0, 100%, 40%);">- * handler as well as using the TSEG region for other purposes. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, num_mtrrs);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return slot;</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *romstage_main(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void romstage_main(unsigned long bist)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- void *romstage_stack_after_car;</span><br><span> const int num_guards = 4;</span><br><span> const u32 stack_guard = 0xdeadbeef;</span><br><span> u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +</span><br><span>@@ -163,10 +118,7 @@</span><br><span> printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Get the stack to use after cache-as-ram is torn down. */</span><br><span style="color: hsl(0, 100%, 40%);">- romstage_stack_after_car = setup_romstage_stack_after_car();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return romstage_stack_after_car;</span><br><span style="color: hsl(120, 100%, 40%);">+ platform_enter_postcar();</span><br><span> }</span><br><span> </span><br><span> void romstage_common(const struct romstage_params *params)</span><br><span>@@ -248,9 +200,3 @@</span><br><span> if (IS_ENABLED(CONFIG_LPC_TPM))</span><br><span> init_tpm(wake_from_s3);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void romstage_after_car(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Load the ramstage. */</span><br><span style="color: hsl(0, 100%, 40%);">- run_ramstage();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig</span><br><span>index 5c8caea..5e6956e 100644</span><br><span>--- a/src/northbridge/intel/haswell/Kconfig</span><br><span>+++ b/src/northbridge/intel/haswell/Kconfig</span><br><span>@@ -21,6 +21,8 @@</span><br><span> select INTEL_GMA_ACPI</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> if NORTHBRIDGE_INTEL_HASWELL</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>index c6d6b2e..055c2a8 100644</span><br><span>--- a/src/northbridge/intel/haswell/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>@@ -36,4 +36,6 @@</span><br><span> mrc.bin-position := 0xfffa0000</span><br><span> mrc.bin-type := mrc</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26793">change 26793</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26793"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9 </div>
<div style="display:none"> Gerrit-Change-Number: 26793 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>