<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26799">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/releases: Add release notes<br><br>This adds the release notes for all of our old releases that have notes<br>to the documentation directory. The release notes for the next release,<br>4.9 is added here as well.<br><br>I would request that people document their changes for the next release<br>themselves if they wish them to be in the release notes.<br><br>Change-Id: I7440a3130f2f7d80c4434d2b5a918e62bbd08fbb<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M Documentation/index.md<br>A Documentation/releases/coreboot-4.1-relnotes.md<br>A Documentation/releases/coreboot-4.2-relnotes.md<br>A Documentation/releases/coreboot-4.3-relnotes.md<br>A Documentation/releases/coreboot-4.4-relnotes.md<br>A Documentation/releases/coreboot-4.5-relnotes.md<br>A Documentation/releases/coreboot-4.6-relnotes.md<br>A Documentation/releases/coreboot-4.7-relnotes.md<br>A Documentation/releases/coreboot-4.8.1-relnotes.md<br>A Documentation/releases/coreboot-4.9-relnotes.md<br>A Documentation/releases/index.md<br>11 files changed, 1,649 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/26799/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/index.md b/Documentation/index.md</span><br><span>index afe892d..4ec4550 100644</span><br><span>--- a/Documentation/index.md</span><br><span>+++ b/Documentation/index.md</span><br><span>@@ -18,3 +18,4 @@</span><br><span> * [System on Chip-specific documentation](soc/index.md)</span><br><span> * [Mainboard-specific documentation](mainboard/index.md)</span><br><span> * [SuperIO-specific documentation](superio/index.md)</span><br><span style="color: hsl(120, 100%, 40%);">+* [Release notes for past releases](releases/index.md)</span><br><span>diff --git a/Documentation/releases/coreboot-4.1-relnotes.md b/Documentation/releases/coreboot-4.1-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..4bc7a39</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.1-relnotes.md</span><br><span>@@ -0,0 +1,58 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Announcing coreboot 4.1</span><br><span style="color: hsl(120, 100%, 40%);">+=======================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Dear coreboot community,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+It has been more than 5 years since we have "released" coreboot 4.0.</span><br><span style="color: hsl(120, 100%, 40%);">+That last release marked some very important milestones that we</span><br><span style="color: hsl(120, 100%, 40%);">+originally prototyped in the abandoned LinuxBIOS v3 efforts, like the</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot filesystem (CBFS), Kconfig support, and (strictly) separate</span><br><span style="color: hsl(120, 100%, 40%);">+device trees, build logic and configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Since then there have been as many significant original developments,</span><br><span style="color: hsl(120, 100%, 40%);">+such as support for many new architectures (ARM, ARM64, MIPS, RISC-V),</span><br><span style="color: hsl(120, 100%, 40%);">+and related architectural changes like access to non-memory mapped SPI</span><br><span style="color: hsl(120, 100%, 40%);">+flash, or better insight about the internals of coreboot at runtime</span><br><span style="color: hsl(120, 100%, 40%);">+through the cbmem console, timestamp collection, or code coverage</span><br><span style="color: hsl(120, 100%, 40%);">+support.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+It became clear that a new release is overdue. With our new release</span><br><span style="color: hsl(120, 100%, 40%);">+process only slowly getting in shape, I decided to take a random commit</span><br><span style="color: hsl(120, 100%, 40%);">+and call it 4.1.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The release itself happens at an arbitrary point in time, but will serve</span><br><span style="color: hsl(120, 100%, 40%);">+as a starting point for other activities that require some kind of</span><br><span style="color: hsl(120, 100%, 40%);">+starting point to build on, described below.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Future releases will happen more frequently, and with more guarantees</span><br><span style="color: hsl(120, 100%, 40%);">+about the state of the release, like having a cool down phase where</span><br><span style="color: hsl(120, 100%, 40%);">+boards can be tested and so on. I plan to create a release every three</span><br><span style="color: hsl(120, 100%, 40%);">+months, so the changes between any two release don't become too</span><br><span style="color: hsl(120, 100%, 40%);">+overwhelming.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+With the release of coreboot 4.1, you get an announcement (this email),</span><br><span style="color: hsl(120, 100%, 40%);">+a git tag (4.1), and tar archives at http://www.coreboot.org/releases/,</span><br><span style="color: hsl(120, 100%, 40%);">+for the coreboot sources and the redistributable blobs.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Starting with coreboot 4.1, we will maintain a high level changelog and</span><br><span style="color: hsl(120, 100%, 40%);">+'flag days' document. The latter will provide a concise list of changes</span><br><span style="color: hsl(120, 100%, 40%);">+which went into coreboot that require chipset or mainboard code to</span><br><span style="color: hsl(120, 100%, 40%);">+change to keep it working with the latest upstream coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+For the time being, I will run these efforts, but I'll happily share</span><br><span style="color: hsl(120, 100%, 40%);">+documentation duties with somebody else. It is a great opportunity to</span><br><span style="color: hsl(120, 100%, 40%);">+keep track of things, learn about the project and its design and various</span><br><span style="color: hsl(120, 100%, 40%);">+internals, while contributing to the project without the need to code.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Please contact me (for example by email or on IRC) if you're interested,</span><br><span style="color: hsl(120, 100%, 40%);">+and we'll work out how to collaborate on this.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The process should enable users of coreboot to follow releases if they</span><br><span style="color: hsl(120, 100%, 40%);">+want a more static base to build on, while making it easier to follow</span><br><span style="color: hsl(120, 100%, 40%);">+along with new developments by providing upgrade documentation.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Since moving away from a rolling (non-)release model is new for</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot, things may still be a bit rough around the edges, but I'll</span><br><span style="color: hsl(120, 100%, 40%);">+provide support for any issues that arise from the release process.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Patrick</span><br><span>diff --git a/Documentation/releases/coreboot-4.2-relnotes.md b/Documentation/releases/coreboot-4.2-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..4d6c670</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.2-relnotes.md</span><br><span>@@ -0,0 +1,182 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Announcing coreboot 4.2</span><br><span style="color: hsl(120, 100%, 40%);">+=======================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Halloween 2015 release - just as scary as that sounds</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Dear coreboot community,</span><br><span style="color: hsl(120, 100%, 40%);">+today marks the release of coreboot 4.2, the second release on our time</span><br><span style="color: hsl(120, 100%, 40%);">+based release schedule. Since 4.1 there were 936 commits by 90 authors,</span><br><span style="color: hsl(120, 100%, 40%);">+increasing the code base by approximately 17000 lines of code. We saw 35</span><br><span style="color: hsl(120, 100%, 40%);">+new contributors - welcome to coreboot! More than 34 developers were</span><br><span style="color: hsl(120, 100%, 40%);">+active as reviewers in that period. Thanks go to all contributors who</span><br><span style="color: hsl(120, 100%, 40%);">+helped shape this release.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+As with 4.1, the release tarballs are available at</span><br><span style="color: hsl(120, 100%, 40%);">+http://www.coreboot.org/releases/. There's also a 4.2 tag and branch in</span><br><span style="color: hsl(120, 100%, 40%);">+the git repository.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This marks the first release that features a changelog comparing it to</span><br><span style="color: hsl(120, 100%, 40%);">+the previous release. There was some limited testing to make sure that</span><br><span style="color: hsl(120, 100%, 40%);">+the code is usable, and it boots on some devices. A structured test plan</span><br><span style="color: hsl(120, 100%, 40%);">+will only become part of the release procedure of future versions. I'm</span><br><span style="color: hsl(120, 100%, 40%);">+grateful to Martin for assembling this release's changelog.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This is also the first release that will be followed by the removal of</span><br><span style="color: hsl(120, 100%, 40%);">+old, unused code. There will be a policy on how to announce deprecation</span><br><span style="color: hsl(120, 100%, 40%);">+and removal of mainboard and chipset code for future releases.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Regards,</span><br><span style="color: hsl(120, 100%, 40%);">+Patrick</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Log of commit d5e6618a4f076610e683b174c4dd5108d960c785 to</span><br><span style="color: hsl(120, 100%, 40%);">+commit 439a527014fa0cb3e4ef60ba59e5c57c737b4444</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Changes between 4.1 and 4.2</span><br><span style="color: hsl(120, 100%, 40%);">+---------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Build system:</span><br><span style="color: hsl(120, 100%, 40%);">+* Store a minimized coreboot config file in cbfs instead of the full</span><br><span style="color: hsl(120, 100%, 40%);">+ config</span><br><span style="color: hsl(120, 100%, 40%);">+* Store the payload config and revision in CBFS when that info is</span><br><span style="color: hsl(120, 100%, 40%);">+ available</span><br><span style="color: hsl(120, 100%, 40%);">+* Add -compression option for cbfs-files-y. Valid entries are now -file,</span><br><span style="color: hsl(120, 100%, 40%);">+ -type, -align, and -compression</span><br><span style="color: hsl(120, 100%, 40%);">+* Change Microcode inclusion method from building .h files to pre-built</span><br><span style="color: hsl(120, 100%, 40%);">+ binaries</span><br><span style="color: hsl(120, 100%, 40%);">+* Update Builder tests for each commit to test utilities and run lint</span><br><span style="color: hsl(120, 100%, 40%);">+ tools</span><br><span style="color: hsl(120, 100%, 40%);">+* Many other small makefile and build changes and fixes</span><br><span style="color: hsl(120, 100%, 40%);">+* Remove expert mode as a Kconfig option</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Utilities:</span><br><span style="color: hsl(120, 100%, 40%);">+* Many fixes and updates to many utilities (158 total commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* ifdtool: Update for skylake, handle region masks correctly</span><br><span style="color: hsl(120, 100%, 40%);">+* crossgcc: Update to gcc 5.2.0</span><br><span style="color: hsl(120, 100%, 40%);">+* kconfig: Add strict mode to fail on kconfig errors and warnings</span><br><span style="color: hsl(120, 100%, 40%);">+* vgabios: Significant fixes to remove issues in linking into coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+ code</span><br><span style="color: hsl(120, 100%, 40%);">+* Add script to parse MAINTAINERS file</span><br><span style="color: hsl(120, 100%, 40%);">+* Add Kconfig lint tool</span><br><span style="color: hsl(120, 100%, 40%);">+* Create a common library to share coreboot routines with utilities</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#### Significant changes and cleanup to cbfstool (81 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Update cbfstool to change the internal location of FSP binaries when</span><br><span style="color: hsl(120, 100%, 40%);">+ adding them</span><br><span style="color: hsl(120, 100%, 40%);">+* Decompress stage files on extraction and turn them into ELF binaries</span><br><span style="color: hsl(120, 100%, 40%);">+* Header sizes are now variable, containing extended attributes</span><br><span style="color: hsl(120, 100%, 40%);">+* Add compression tags to all cbfs headers so all cbfs files can be</span><br><span style="color: hsl(120, 100%, 40%);">+ compressed</span><br><span style="color: hsl(120, 100%, 40%);">+* Add and align CBFS components in one pass instead of two</span><br><span style="color: hsl(120, 100%, 40%);">+* Add XIP support for X86 to relocate the romstage when it'™s added</span><br><span style="color: hsl(120, 100%, 40%);">+* Removed locate command as it'™s no longer needed</span><br><span style="color: hsl(120, 100%, 40%);">+* Add bootblock and cbfs_header file types so the master header knows</span><br><span style="color: hsl(120, 100%, 40%);">+ about them</span><br><span style="color: hsl(120, 100%, 40%);">+* Prefer FMAP data to CBFS master header if FMAP data exists</span><br><span style="color: hsl(120, 100%, 40%);">+* Add hashes to cbfs file metadata for verification of images</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Payloads:</span><br><span style="color: hsl(120, 100%, 40%);">+* SeaBIOS: update stable release from 1.7.5 to 1.8.2</span><br><span style="color: hsl(120, 100%, 40%);">+* Libpayload had some significant changes (61 commits). Major changes:</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for fmap tables</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for SuperSpeed (3.0) USB hubs</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates and bugfixes for DesignWare OTG controller (DWC2)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add video_printf to print text with specified foreground & background</span><br><span style="color: hsl(120, 100%, 40%);">+ colors</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates to match changes to cbfs/cbfstool</span><br><span style="color: hsl(120, 100%, 40%);">+* Add cbgfx, a library to show graphics and text on a display</span><br><span style="color: hsl(120, 100%, 40%);">+* Read cbfs offset and size from sysinfo when available</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Vendorcode:</span><br><span style="color: hsl(120, 100%, 40%);">+* fsp_baytrail: Support Baytrail FSP Gold 4 release</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD binary PI: add support for fan control</span><br><span style="color: hsl(120, 100%, 40%);">+* Work to get AMD AGESA to compile correctly as 64-bit code</span><br><span style="color: hsl(120, 100%, 40%);">+* Add standalone (XIP) verstage support for x86 to verify romstage</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Mainboards:</span><br><span style="color: hsl(120, 100%, 40%);">+* New Mainboards:</span><br><span style="color: hsl(120, 100%, 40%);">+* apple/macbookair4_2 * Sandy/Ivy Bridge with Panther / Cougar point</span><br><span style="color: hsl(120, 100%, 40%);">+chipset</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kgpe-d16 - AMD Family 10, SB700/SR5650 platform</span><br><span style="color: hsl(120, 100%, 40%);">+* emulation/spike-riscv - RISCV virtualized platform</span><br><span style="color: hsl(120, 100%, 40%);">+* google/chell - Intel Skylake chrome platform</span><br><span style="color: hsl(120, 100%, 40%);">+* google/cyan - Intel Braswell chrome platform</span><br><span style="color: hsl(120, 100%, 40%);">+* google/glados - Intel Skylake chrome platform</span><br><span style="color: hsl(120, 100%, 40%);">+* google/lars - Intel Skylake chrome platform</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/kunimitsu - Intel Skylake chrome platform</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/sklrvp - Intel Skylake reference platform</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/strago - Intel Braswell chrome platform</span><br><span style="color: hsl(120, 100%, 40%);">+* Cleanups of many mainboards - several patches each for:</span><br><span style="color: hsl(120, 100%, 40%);">+* amd/bettong</span><br><span style="color: hsl(120, 100%, 40%);">+* getac/p470</span><br><span style="color: hsl(120, 100%, 40%);">+* google/auron, google/smaug and google/veyron_rialto</span><br><span style="color: hsl(120, 100%, 40%);">+* pcengines/apu1</span><br><span style="color: hsl(120, 100%, 40%);">+* siemens/mc_tcu3</span><br><span style="color: hsl(120, 100%, 40%);">+* Combine the google/veyron_(jerry, mighty, minnie, pinkie, shark &</span><br><span style="color: hsl(120, 100%, 40%);">+ speedy) mainboards into the single google/veyron mainboard directory</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Console:</span><br><span style="color: hsl(120, 100%, 40%);">+* Add EM100 ˜hyper term" spi console support in ramstage & smm</span><br><span style="color: hsl(120, 100%, 40%);">+* Add console support for verstage</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### ARM:</span><br><span style="color: hsl(120, 100%, 40%);">+* armv7: use asm coded memory operations for 32/16 bit read/write</span><br><span style="color: hsl(120, 100%, 40%);">+* Many cleanups to the nvidia tegra chips (40 patches)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### RISC-V:</span><br><span style="color: hsl(120, 100%, 40%);">+* Add trap handling</span><br><span style="color: hsl(120, 100%, 40%);">+* Add virtual Memory setup</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### X86:</span><br><span style="color: hsl(120, 100%, 40%);">+* Remove and re-add Rangeley and Ivy Bridge / panther point FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ platforms</span><br><span style="color: hsl(120, 100%, 40%);">+* Update microcode update parser to use stock AMD microcode blobs from</span><br><span style="color: hsl(120, 100%, 40%);">+ CBFS</span><br><span style="color: hsl(120, 100%, 40%);">+* ACPI: Align FACS to 64 byte boundary. Fixes FWTS error</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD/SB700: Init devices in early boot, restore power state after power</span><br><span style="color: hsl(120, 100%, 40%);">+ failure. Add IDE/SATA asl code</span><br><span style="color: hsl(120, 100%, 40%);">+* Add initial support for AMD Socket G34 processors</span><br><span style="color: hsl(120, 100%, 40%);">+* Add tick frequency to timestamp table to calculate boot times more</span><br><span style="color: hsl(120, 100%, 40%);">+ accurately</span><br><span style="color: hsl(120, 100%, 40%);">+* Unify X86 romstage / ramstage linking to match other platforms</span><br><span style="color: hsl(120, 100%, 40%);">+* Start preparing X86 bootblock for non-memory-mapped BIOS media</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/amd/car: Add Suspend to RAM (S3) support</span><br><span style="color: hsl(120, 100%, 40%);">+* Native VGA init fixes on several platforms</span><br><span style="color: hsl(120, 100%, 40%);">+* Significant updates to FSP 1.1 code for cleanup and cbfstool changes</span><br><span style="color: hsl(120, 100%, 40%);">+* SMMhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG to</span><br><span style="color: hsl(120, 100%, 40%);">+ prevent the memory sinkhole smm hack</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Drivers:</span><br><span style="color: hsl(120, 100%, 40%);">+* Add native text mode support for the Aspeed AST2050</span><br><span style="color: hsl(120, 100%, 40%);">+* w83795: Add support for for fan control and voltage monitoring</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel GMA ACPI consolidation and improvements</span><br><span style="color: hsl(120, 100%, 40%);">+* Set up the 8254 timer before running option ROMs</span><br><span style="color: hsl(120, 100%, 40%);">+* Resource allocator: Page align memory mapped PCI resources</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Lib:</span><br><span style="color: hsl(120, 100%, 40%);">+* Derive fmap name from offset/size</span><br><span style="color: hsl(120, 100%, 40%);">+* Several edid fixes</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates to cbfs matching changes in cbfstool</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Submodules:</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+### 3rdparty/blobs:</span><br><span style="color: hsl(120, 100%, 40%);">+Total commits: 16</span><br><span style="color: hsl(120, 100%, 40%);">+Log of commit 61d663e3 to commit aab093f0</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)</span><br><span style="color: hsl(120, 100%, 40%);">+* Update microcode to binary blobs. Remove old .h microcode files</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### 3rdparty/arm-trusted-firmware:</span><br><span style="color: hsl(120, 100%, 40%);">+* No Changes</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### 3rdparty/vboot:</span><br><span style="color: hsl(120, 100%, 40%);">+Total commits: 41</span><br><span style="color: hsl(120, 100%, 40%);">+Log of commit fbf631c8 to commit d6723ed1</span><br><span style="color: hsl(120, 100%, 40%);">+* Update the code to determine the write protect line gpio value</span><br><span style="color: hsl(120, 100%, 40%);">+* Several updates to futility and image_signing scripts</span><br><span style="color: hsl(120, 100%, 40%);">+* Update crossystem to accommodate Android mosys location</span><br><span style="color: hsl(120, 100%, 40%);">+* Support reboot requested by secdata</span><br><span style="color: hsl(120, 100%, 40%);">+* Add NV flag to default boot legacy OS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### util/nvidia/cbootimage:</span><br><span style="color: hsl(120, 100%, 40%);">+* No Changes</span><br><span>diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..2a5591c</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.3-relnotes.md</span><br><span>@@ -0,0 +1,183 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Announcing coreboot 4.3</span><br><span style="color: hsl(120, 100%, 40%);">+=======================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The "Oh, has FOSDEM started?" release</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Dear coreboot community,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+today marks the release of coreboot 4.3, the third release on our time</span><br><span style="color: hsl(120, 100%, 40%);">+based release schedule. Since the last release, 1030 commits by 114</span><br><span style="color: hsl(120, 100%, 40%);">+authors added a net total of 17500 lines to the source code. Thank you</span><br><span style="color: hsl(120, 100%, 40%);">+to all who contributed!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The release tarballs are available at http://www.coreboot.org/releases/.</span><br><span style="color: hsl(120, 100%, 40%);">+There's also a 4.3 tag and branch in the git repository.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Besides the usual addition of new mainboards (14) and chipsets</span><br><span style="color: hsl(120, 100%, 40%);">+(various), a big theme of the development since 4.2 was cleaning up the</span><br><span style="color: hsl(120, 100%, 40%);">+code: 20 mainboards were removed that aren't on the market for years</span><br><span style="color: hsl(120, 100%, 40%);">+(and even hard to get on Ebay). For several parts of the tree, we</span><br><span style="color: hsl(120, 100%, 40%);">+established tighter controls, making errors out of what were warnings</span><br><span style="color: hsl(120, 100%, 40%);">+(and cleaning up the code to match) and provided better tests for</span><br><span style="color: hsl(120, 100%, 40%);">+various aspects of the tree, and in general tried to establish a more</span><br><span style="color: hsl(120, 100%, 40%);">+consistent structure across the code base.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Besides that, we had various improvements across the tree, each</span><br><span style="color: hsl(120, 100%, 40%);">+important when using the hardware, but to numerous for individual shout</span><br><span style="color: hsl(120, 100%, 40%);">+outs. Martin compiled a list that's best posted verbatim. Thanks Martin!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Log of commit 529fd81f640fa514ea4c443dd561086e7c582a64 to commit</span><br><span style="color: hsl(120, 100%, 40%);">+1bf5e6409678d04fd15f9625460078853118521c for a total of 1030 commits:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 14 mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kfsn4-dre_k8: Native init Dual AMD K8 CPUs & Nvidia CK804</span><br><span style="color: hsl(120, 100%, 40%);">+ southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+* esd/atom15: Bay Trail SOC mainboard using Intel's FSP</span><br><span style="color: hsl(120, 100%, 40%);">+* gigabyte/ga-g41m-es2l: Intel Core 2 / Native init x4x NB / I82801GX SB</span><br><span style="color: hsl(120, 100%, 40%);">+* google/guado: Intel Broadwell chromebox (Asus Chromebox CN62)</span><br><span style="color: hsl(120, 100%, 40%);">+* google/oak: Mediatek MT8173 SoC chromebook</span><br><span style="color: hsl(120, 100%, 40%);">+* google/tidus: Intel Broadwell chromebox (Lenovo ThinkCentre Chromebox)</span><br><span style="color: hsl(120, 100%, 40%);">+* google/veyron_emile: Rockchip RK3288 SoC board</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/d510mo: Native init Intel Pineview with Intel I82801GX</span><br><span style="color: hsl(120, 100%, 40%);">+ southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/littleplains: Intel Atom c2000 (Rangeley) SoC board</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/stargo2: Intel Ivy Bridge / Cave Creek usint Intel's FSP</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/r400: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/t500: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB</span><br><span style="color: hsl(120, 100%, 40%);">+* purism/librem13: Intel Broadwell Laptop using Intel MRC</span><br><span style="color: hsl(120, 100%, 40%);">+* sunw/ultra40m2: Native init Dual AMD K8 Processors & Nvidia MCP55 SB</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Removed 20 mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* arima/hdama</span><br><span style="color: hsl(120, 100%, 40%);">+* digitallogic/adl855pc</span><br><span style="color: hsl(120, 100%, 40%);">+* ibm/e325, e326</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/sklrvp</span><br><span style="color: hsl(120, 100%, 40%);">+* iwill/dk8s2, dk8x</span><br><span style="color: hsl(120, 100%, 40%);">+* newisys/khepri</span><br><span style="color: hsl(120, 100%, 40%);">+* tyan/s2735, s2850, s2875, s2880, s2881 & s2882</span><br><span style="color: hsl(120, 100%, 40%);">+* tyan/s2885, s2891, s2892, s2895, s4880 & s4882</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Improvements to mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* amd/bettong: fixes to Interrupts, Memory config, S4, EMMC, UARTS</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kgpe-d16: IOMMU and memory fixes, Add CMOS options, Enable GART</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/strago: GPIO, DDR, & SD config, FSP updates, Clock fixes</span><br><span style="color: hsl(120, 100%, 40%);">+* ACPI fixes across various platforms</span><br><span style="color: hsl(120, 100%, 40%);">+* Many individual fixes to other mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Continued updates for the Intel Skylake platform</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* google/chell, glados, & lars: FSP & Memory updates, Add Fan & NHLT</span><br><span style="color: hsl(120, 100%, 40%);">+ support</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/kunimitsu: FSP & GPIO updates, Add Fan & NHLT (audio) support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Build system</span><br><span style="color: hsl(120, 100%, 40%);">+------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Update build to use FMAP based firmware layout with multiple cbfs</span><br><span style="color: hsl(120, 100%, 40%);">+ sections</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable Kconfig strict mode - Kconfig warnings are no longer allowed.</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable ACPI warnings are errors in IASL - warnings are no longer</span><br><span style="color: hsl(120, 100%, 40%);">+ allowed.</span><br><span style="color: hsl(120, 100%, 40%);">+* Tighten checking on toolchains and give feedback to users if there are</span><br><span style="color: hsl(120, 100%, 40%);">+ issues</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates to get the ADA compiler to work correctly for coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+* Various improvements to Makefiles and build scripts</span><br><span style="color: hsl(120, 100%, 40%);">+* Cleanup of CBFS file handling</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Utilities</span><br><span style="color: hsl(120, 100%, 40%);">+---------</span><br><span style="color: hsl(120, 100%, 40%);">+* cleanups and improvements to many of the utilities</span><br><span style="color: hsl(120, 100%, 40%);">+* cbfstool: Many fixes and extensions to integrate with FMAP</span><br><span style="color: hsl(120, 100%, 40%);">+* Add amdfwtool to combine AMD firmware blobs instead of using shell</span><br><span style="color: hsl(120, 100%, 40%);">+ scripts.</span><br><span style="color: hsl(120, 100%, 40%);">+* Toolchain updates: new versions of GMP & MPFR. Add ADA.</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates for building on NetBSD & OS X</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Payloads</span><br><span style="color: hsl(120, 100%, 40%);">+--------</span><br><span style="color: hsl(120, 100%, 40%);">+* SeaBIOS: Update stable release to 1.9.0</span><br><span style="color: hsl(120, 100%, 40%);">+* coreinfo: fix date, hide cursor, use crosscompiler to build</span><br><span style="color: hsl(120, 100%, 40%);">+* libpayload: updates for cbfs, XHCI and DesignWare HCD controllers</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ARM</span><br><span style="color: hsl(120, 100%, 40%);">+---</span><br><span style="color: hsl(120, 100%, 40%);">+* Added 1 soc: mediatek/mt8173</span><br><span style="color: hsl(120, 100%, 40%);">+* Various fixes for ARM64 platforms</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+X86</span><br><span style="color: hsl(120, 100%, 40%);">+---</span><br><span style="color: hsl(120, 100%, 40%);">+* Added 2 northbridges: intel/pineview & x4x</span><br><span style="color: hsl(120, 100%, 40%);">+* Removed 1 northbridge: intel/i440lx</span><br><span style="color: hsl(120, 100%, 40%);">+* Added 1 southbridge: intel/fsp_i89xx</span><br><span style="color: hsl(120, 100%, 40%);">+* Removed 2 southbridge(s): intel/esb6300 & i82801cx</span><br><span style="color: hsl(120, 100%, 40%);">+* Rename amd/model_10xxx to family_10h-family_15h.</span><br><span style="color: hsl(120, 100%, 40%);">+* ACPI: fix warnings, Add functions for IVRS, DMAR I/O-APIC and HPET</span><br><span style="color: hsl(120, 100%, 40%);">+ entries</span><br><span style="color: hsl(120, 100%, 40%);">+* Work in many areas fixing issues compiling in 64-bit</span><br><span style="color: hsl(120, 100%, 40%);">+* Numerous other fixes across the tree</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Areas with significant work on updates and fixes</span><br><span style="color: hsl(120, 100%, 40%);">+------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/amd/model_fxx</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other</span><br><span style="color: hsl(120, 100%, 40%);">+ changes</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other</span><br><span style="color: hsl(120, 100%, 40%);">+ changes</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/intel/sandybridge: Add IOMMU & ACPI DMAR support, Memory cleanup</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/intel/braswell: FSP & ACPI updates, GPIO & clock Fixes</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/intel/fsp_baytrail: GPIO, microcode and Interrupt updates.</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/intel/skylake: FSP, Power/Thermal & GPIO Updates, Add NHLT support</span><br><span style="color: hsl(120, 100%, 40%);">+* sb/amd/sb700: Add ACPI & CMOS Setting support, SATA & clock Fixes</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+MIPS</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+* Imgtec Pistachio: Memory, PLL & I2C fixes, add reset</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SuperIO</span><br><span style="color: hsl(120, 100%, 40%);">+-------</span><br><span style="color: hsl(120, 100%, 40%);">+* Expand functionality for ite/it8718f & nuvoton/nct5572d superio</span><br><span style="color: hsl(120, 100%, 40%);">+ devices</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 3 SIOs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/i8900</span><br><span style="color: hsl(120, 100%, 40%);">+* winbond/w83667hg-a & wpcd376i</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Removed 6 SIOs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* fintek/f71889</span><br><span style="color: hsl(120, 100%, 40%);">+* ite/it8661f</span><br><span style="color: hsl(120, 100%, 40%);">+* nsc/pc8374 & pc97307</span><br><span style="color: hsl(120, 100%, 40%);">+* nuvoton/nct6776</span><br><span style="color: hsl(120, 100%, 40%);">+* smsc/fdc37m60x</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Lib</span><br><span style="color: hsl(120, 100%, 40%);">+---</span><br><span style="color: hsl(120, 100%, 40%);">+* Several updates for reading EDID tables</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+MISC</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+* Commonlib: continued updates for cbfs changes</span><br><span style="color: hsl(120, 100%, 40%);">+* Work on getting license headers on all coreboot files</span><br><span style="color: hsl(120, 100%, 40%);">+* Drop the third paragraph of GPL copyright header across all of</span><br><span style="color: hsl(120, 100%, 40%);">+ coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Submodules</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/blobs: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot statistics</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------</span><br><span style="color: hsl(120, 100%, 40%);">+Total commits: 1030</span><br><span style="color: hsl(120, 100%, 40%);">+Total authors: 114</span><br><span style="color: hsl(120, 100%, 40%);">+New authors: 46</span><br><span style="color: hsl(120, 100%, 40%);">+Total Reviewers: 41</span><br><span style="color: hsl(120, 100%, 40%);">+Total lines added: 88255</span><br><span style="color: hsl(120, 100%, 40%);">+Total lines removed: -70735</span><br><span style="color: hsl(120, 100%, 40%);">+Total delta: 17520</span><br><span>diff --git a/Documentation/releases/coreboot-4.4-relnotes.md b/Documentation/releases/coreboot-4.4-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..8b67f5f</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.4-relnotes.md</span><br><span>@@ -0,0 +1,110 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Announcing coreboot 4.4</span><br><span style="color: hsl(120, 100%, 40%);">+=======================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+We are happy to announce the release of coreboot 4.4. This is our</span><br><span style="color: hsl(120, 100%, 40%);">+fourth quarterly release. Since the last release, we've had 850 commits</span><br><span style="color: hsl(120, 100%, 40%);">+by 90 authors adding 59000 lines to the codebase.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The release tarballs are available at https://www.coreboot.org/releases/</span><br><span style="color: hsl(120, 100%, 40%);">+There is a 4.4 tag and branch in the git repository.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Log of commit 3141eac900 to commit 588ccaa9a7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Major areas that received significant changes in for this release:</span><br><span style="color: hsl(120, 100%, 40%);">+* Build system (30 commits) - Add postcar stage, 'timeless' builds,</span><br><span style="color: hsl(120, 100%, 40%);">+ extend site-local, test toolchain by version string, update</span><br><span style="color: hsl(120, 100%, 40%);">+ dependencies, catch ACPI errors, add additional macros.</span><br><span style="color: hsl(120, 100%, 40%);">+* Toolchain updates (40+ patches) - Update IASL to v20160318 , LLVM to</span><br><span style="color: hsl(120, 100%, 40%);">+ v3.7.1, add GNU make, add nds32le GCC compiler</span><br><span style="color: hsl(120, 100%, 40%);">+* Lint tools (30 patches) - Update existing lint utilities, add lint</span><br><span style="color: hsl(120, 100%, 40%);">+ tests for executable bit, make sure site-local isn't committed, add</span><br><span style="color: hsl(120, 100%, 40%);">+ test to break all lint tests.</span><br><span style="color: hsl(120, 100%, 40%);">+* Payloads (60 commits) - Fixes for libpayload, coreinfo and nvramcui,</span><br><span style="color: hsl(120, 100%, 40%);">+ add new payloads, see below.</span><br><span style="color: hsl(120, 100%, 40%);">+* Maintainers file - (8 patches) - continue adding maintainers for</span><br><span style="color: hsl(120, 100%, 40%);">+ various areas.</span><br><span style="color: hsl(120, 100%, 40%);">+* Documentation for adding Intel FSP-based platforms (20 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 9 mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kcma-d8</span><br><span style="color: hsl(120, 100%, 40%);">+* emulation/qemu-power8</span><br><span style="color: hsl(120, 100%, 40%);">+* google/auron_paine</span><br><span style="color: hsl(120, 100%, 40%);">+* google/gru</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/amenia</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/apollolake_rvp</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/camelbackmountain_fsp</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/galileo</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/t420</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Existing boards with significant updates</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kgpe-d16</span><br><span style="color: hsl(120, 100%, 40%);">+* google/oak</span><br><span style="color: hsl(120, 100%, 40%);">+* google/chell</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/kunimitsu</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Changes in chips</span><br><span style="color: hsl(120, 100%, 40%);">+----------------</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 1 new architecture</span><br><span style="color: hsl(120, 100%, 40%);">+* power8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 1 processor</span><br><span style="color: hsl(120, 100%, 40%);">+* qemu-power8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 5 socs</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/fsp_broadwell_de</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/quark</span><br><span style="color: hsl(120, 100%, 40%);">+* marvell/armada38x</span><br><span style="color: hsl(120, 100%, 40%);">+* rockchip/rk3399</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Existing chip areas with many changes</span><br><span style="color: hsl(120, 100%, 40%);">+* cpuamd/mct_ddr3</span><br><span style="color: hsl(120, 100%, 40%);">+* drivers/intel/fsp2_0</span><br><span style="color: hsl(120, 100%, 40%);">+* northbridge/intel/sandybridge/raminit</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/intel/fsp_baytrail</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+* soc/mediatek/mt8173</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 1 new vendorcode directory</span><br><span style="color: hsl(120, 100%, 40%);">+* siemens</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Submodules</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 1 submodule</span><br><span style="color: hsl(120, 100%, 40%);">+* chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Updated 3 submodules</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/arm-trusted-firmware (329 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/vboot (28 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* util/nvidia/cbootimage (13 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Other</span><br><span style="color: hsl(120, 100%, 40%);">+-----</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 4 payloads</span><br><span style="color: hsl(120, 100%, 40%);">+* depthcharge: For ChromeOS verified boot</span><br><span style="color: hsl(120, 100%, 40%);">+* iPXE: For network booting</span><br><span style="color: hsl(120, 100%, 40%);">+* Memtest86+: Updated with fixes for correctly testing coreboot with</span><br><span style="color: hsl(120, 100%, 40%);">+ payloads</span><br><span style="color: hsl(120, 100%, 40%);">+* U-Boot (Experimental): Alternate payload for booting an OS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 6 utilities</span><br><span style="color: hsl(120, 100%, 40%);">+* archive - Concatenates files into a single blob with an indexed header</span><br><span style="color: hsl(120, 100%, 40%);">+* chromeos - Download and extract blobs from a ChromeOS image</span><br><span style="color: hsl(120, 100%, 40%);">+* futility - vboot Firmware utility</span><br><span style="color: hsl(120, 100%, 40%);">+* intelmetool - Shows information about the Intel ME on a platform.</span><br><span style="color: hsl(120, 100%, 40%);">+* marvell/doimage_mv - No usage notes</span><br><span style="color: hsl(120, 100%, 40%);">+* post - Simple utility to test post cards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot statistics</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Commits: 850</span><br><span style="color: hsl(120, 100%, 40%);">+* Total authors: 90</span><br><span style="color: hsl(120, 100%, 40%);">+* New authors: 28</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Reviewers: 40</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Submitters: 17</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines added: 74054</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines removed: -15056</span><br><span style="color: hsl(120, 100%, 40%);">+* Total difference: 58998</span><br><span>diff --git a/Documentation/releases/coreboot-4.5-relnotes.md b/Documentation/releases/coreboot-4.5-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..31eac0a</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.5-relnotes.md</span><br><span>@@ -0,0 +1,214 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Announcing coreboot 4.5</span><br><span style="color: hsl(120, 100%, 40%);">+=======================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+We are happy to announce the release of coreboot 4.5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The 4.5 release covers commit 80a3df260767 to commit 0bc12abc2b26.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This release is the first since the project switched from doing</span><br><span style="color: hsl(120, 100%, 40%);">+quarterly releases to doing biannual releases. The next release will be</span><br><span style="color: hsl(120, 100%, 40%);">+in April of 2017.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Since the last release in April, the coreboot project has had 1889</span><br><span style="color: hsl(120, 100%, 40%);">+commits by 119 authors.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The release tarballs and gpg signatures are available in the usual place</span><br><span style="color: hsl(120, 100%, 40%);">+at https://www.coreboot.org/downloads</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There is a 4.5 tag in the git repository, and a branch will be created</span><br><span style="color: hsl(120, 100%, 40%);">+as needed.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Areas with significant updates</span><br><span style="color: hsl(120, 100%, 40%);">+------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Toolchain (29 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated mpfr version from 3.1.3 to 3.1.4</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated gcc version from 5.2.0 to 5.3.0</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated binutils version from 2.25 to 2.26.1 & Fix aarch64 build</span><br><span style="color: hsl(120, 100%, 40%);">+ problem</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated gdb version from 7.9.1 to 7.11</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated iasl version from 20160318 to 20160831</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated python version from 3.4.3 to 3.5.1</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated expat version from 2.1.0 to 2.1.1</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated llvm / clang version from 3.7.1 to 3.8.0</span><br><span style="color: hsl(120, 100%, 40%);">+* Updated make version from 4.1 to 4.2.1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Build system (32 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates for cbfstool / fmap changes</span><br><span style="color: hsl(120, 100%, 40%);">+* Order per-region files to optimize placement success</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for the ADA language and toolchain.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Utilities (103 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Lint - Update checkpatch.pl, add tools to find non-ascii &</span><br><span style="color: hsl(120, 100%, 40%);">+ unprintable chars and to verify a single newline at the end of files</span><br><span style="color: hsl(120, 100%, 40%);">+* cbfstool - Update for Linux payloads, Honor FSP modules addresses, fix</span><br><span style="color: hsl(120, 100%, 40%);">+ elf parsing</span><br><span style="color: hsl(120, 100%, 40%);">+* Sconfig - Add 10 bit addressing mode for i2c devices, add generic</span><br><span style="color: hsl(120, 100%, 40%);">+ device type, support strings, pass in devicetree filename</span><br><span style="color: hsl(120, 100%, 40%);">+* General code cleanup (197 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Cleaning up code formatting and whitespace</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix spelling & capitalization</span><br><span style="color: hsl(120, 100%, 40%);">+* Removing commented out code</span><br><span style="color: hsl(120, 100%, 40%);">+* Transition away from device_t</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### TPM (55 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for Trusted Platform Module 2.0</span><br><span style="color: hsl(120, 100%, 40%);">+* SPI & refactored I2C TPM driver</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Drivers (54 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add ACPI support in several drivers</span><br><span style="color: hsl(120, 100%, 40%);">+* coreboot_tables - Extend serial port description</span><br><span style="color: hsl(120, 100%, 40%);">+* Elog - refactor, add debug info</span><br><span style="color: hsl(120, 100%, 40%);">+* I2C - add generic driver,</span><br><span style="color: hsl(120, 100%, 40%);">+* SPI - Add new chip support, major refactoring, don't assume SPI flash</span><br><span style="color: hsl(120, 100%, 40%);">+ boot device</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Lib (33 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add real-time-clock functions</span><br><span style="color: hsl(120, 100%, 40%);">+* Add RW boot device construct</span><br><span style="color: hsl(120, 100%, 40%);">+* reg_script updates: add to bootblock, add xor support, add display</span><br><span style="color: hsl(120, 100%, 40%);">+ support</span><br><span style="color: hsl(120, 100%, 40%);">+* Timestamp fixes & updates</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Vendorcode</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD (14 commits) - Cleanup, add libagesa.a builds, remove unused code.</span><br><span style="color: hsl(120, 100%, 40%);">+* Google (22 commits) - VBoot2 updates and cleanup</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel (86 commits) - Add Intel FSP 2.0, update Broadwell DE support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Payloads (37 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Subpayload support got extend and is enabled by default.</span><br><span style="color: hsl(120, 100%, 40%);">+* nvramcui: refactor, update build</span><br><span style="color: hsl(120, 100%, 40%);">+* SeaBIOS: Update stable version to 1.9.3, add bootorder file</span><br><span style="color: hsl(120, 100%, 40%);">+* iPXE: Update stable version to the last commit of July 2016</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix broken linux boot sequence</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Mainboard changes</span><br><span style="color: hsl(120, 100%, 40%);">+-----------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 13 mainboards, plus a few mainboard variants not included here</span><br><span style="color: hsl(120, 100%, 40%);">+* ADI RCC-DFF networking board (adi/rcc-dff) - intel/rangeley SoC</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD Evaluation Board DB-FT3B-LC (amd/db-ft3b-lc) - amd/00730F01</span><br><span style="color: hsl(120, 100%, 40%);">+ (Family 16h Models 30h-3Fh (Mullins)) CPU</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD f2950 / TONK 1201/2 Board (amd/f2950) - amd/geode_lx CPU</span><br><span style="color: hsl(120, 100%, 40%);">+* Apple iMAC 5.2 (apple/imac52) - intel/i945 CPU</span><br><span style="color: hsl(120, 100%, 40%);">+* Unibap Development Kit ODE E21XX - amd/00730F01 (Family 16h Models</span><br><span style="color: hsl(120, 100%, 40%);">+ 30h-3Fh (Mullins)) CPU</span><br><span style="color: hsl(120, 100%, 40%);">+* elmex/pcm205400 - amd/Family_14 CPU</span><br><span style="color: hsl(120, 100%, 40%);">+* elmex/pcm205401 - amd/Family_14 CPU</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo N21 chromebook (google/enguarde) - intel/baytrail SoC</span><br><span style="color: hsl(120, 100%, 40%);">+* google/gale - Qualcomm IPQ40XX SoC</span><br><span style="color: hsl(120, 100%, 40%);">+* AOpen Chromebox (google/ninja) - intel/baytrail SoC</span><br><span style="color: hsl(120, 100%, 40%);">+* google/reef - intel/apollolake SoC</span><br><span style="color: hsl(120, 100%, 40%);">+* Acer Chromebox CXI2 (google/rikku) - intel/Broadwell SoC</span><br><span style="color: hsl(120, 100%, 40%);">+* google/rotor - marvell/MVMAP2315 SoC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Removed 5 mainboards:</span><br><span style="color: hsl(120, 100%, 40%);">+These were all development boards not available to the public.</span><br><span style="color: hsl(120, 100%, 40%);">+* google/bolt - intel/haswell - removed in commit 139314b</span><br><span style="color: hsl(120, 100%, 40%);">+* google/rush - nvidia/tegra132 - removed in commit e67cd9e</span><br><span style="color: hsl(120, 100%, 40%);">+* google/rush_ryu - nvidia/tegra132 - removed in commit 0c63415</span><br><span style="color: hsl(120, 100%, 40%);">+* google/slippy - intel/haswell - removed in commit bc24b85</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/amenia - intel/apollolake - removed in commit c2586db</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Existing boards with significant updates</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kgpe-d16 - amd/socket_G34 - Add TPM support, enable secondary</span><br><span style="color: hsl(120, 100%, 40%);">+ serial port</span><br><span style="color: hsl(120, 100%, 40%);">+* emulation/spike-riscv: RISC-V -clean up, use generic bootblock, look</span><br><span style="color: hsl(120, 100%, 40%);">+ for CBFS in RAM, reimplement SBI</span><br><span style="color: hsl(120, 100%, 40%);">+* google/gru - rockchip/RK3399 SoC (76 commits) - Board bringup</span><br><span style="color: hsl(120, 100%, 40%);">+* google/oak - mediatek/mt8173 SoC- Add Elm variant, update memory,</span><br><span style="color: hsl(120, 100%, 40%);">+ configure display, initialize touchscreen gpio</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/galilleo- intel/quark SoC (14 commits) - Board bringup, add</span><br><span style="color: hsl(120, 100%, 40%);">+ galileo gen1 support, switch to FSP2.0</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/minnowmax - intel/fsp_baytrail SoC - Enable all PCIe ports,</span><br><span style="color: hsl(120, 100%, 40%);">+ Program GPIO for power LED</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/x60 - intel/socket_mPGA478 - init GPIOs before dock check, add</span><br><span style="color: hsl(120, 100%, 40%);">+ hda verb table</span><br><span style="color: hsl(120, 100%, 40%);">+* siemens/mc_bdx1 - intel/fsp_broadwell_de SoC - Add external RTC, Set</span><br><span style="color: hsl(120, 100%, 40%);">+ up MAC addresses, Update IRQs</span><br><span style="color: hsl(120, 100%, 40%);">+* siemens/mc_tcu3 - intel/fsp_baytrail SoC - cleanup & LCD panel updates</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Changes in chips</span><br><span style="color: hsl(120, 100%, 40%);">+----------------</span><br><span style="color: hsl(120, 100%, 40%);">+### Moved 3 northbridge/southbridge pairs to soc:</span><br><span style="color: hsl(120, 100%, 40%);">+* dmp/vortex86ex</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/sch</span><br><span style="color: hsl(120, 100%, 40%);">+* rdc/r8610</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 2 socs:</span><br><span style="color: hsl(120, 100%, 40%);">+* marvell/mvmap2315 (12 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* qualcomm/ipq40xx (22 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Removed 1 soc:</span><br><span style="color: hsl(120, 100%, 40%);">+* nvidia/tegra132 - removed in commit 9ba0699</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Added 2 sios:</span><br><span style="color: hsl(120, 100%, 40%);">+* nuvoton/nct6776</span><br><span style="color: hsl(120, 100%, 40%);">+* nuvoton/nct6791d</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### ARM (34 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add armv7-r configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#### rockchip/rk3399 (73 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Bringup, memory updates</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### RISC-V (40 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Improve and refactor trap handling</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### X86 (225 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### ACPI (40 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for writing various entries and descriptor</span><br><span style="color: hsl(120, 100%, 40%);">+ types, Add common definitions, Use 'GOOG' id for coreboot table</span><br><span style="color: hsl(120, 100%, 40%);">+* amd/mct_ddr3 northbridge: Support non-ECC DIMMs, Update SMBIOS,</span><br><span style="color: hsl(120, 100%, 40%);">+ various fixes</span><br><span style="color: hsl(120, 100%, 40%);">+* arch/x86: many postcar stage updates, add common ACPI definitions,</span><br><span style="color: hsl(120, 100%, 40%);">+ Support "weak" BIST and timestamp save routines</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/apollolake SoC (211 commits) - Chip bringup, Update bootblock</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/common: ACPI updates, Add smihandler, LPSS I2C driver, and IGD</span><br><span style="color: hsl(120, 100%, 40%);">+ OpRegion support</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/fsp_broadwell_de: IRQ fixes, SPI message fixes, Add DMAR table</span><br><span style="color: hsl(120, 100%, 40%);">+ to ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/gm45 northbridge: Fix text mode init, enable vesa framebuffer,</span><br><span style="color: hsl(120, 100%, 40%);">+ use VGA if connected</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/i945 northbridge: add native VGA init, Update divisor</span><br><span style="color: hsl(120, 100%, 40%);">+ calculations</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/quark SoC (62 commits) - Chip bringup, add Fsp2.0 support,</span><br><span style="color: hsl(120, 100%, 40%);">+ updates for serial console</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/skylake CPU (61 commits) - Finished Skylake bringup, start</span><br><span style="color: hsl(120, 100%, 40%);">+ updating for Kabylake FSP</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/x4x northbridge (13 commits) - Memory & Graphics updates</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Submodules</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+Updated 4 submodules</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/blobs (6 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/arm-trusted-firmware (425 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/vboot (61 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/chromeec/ (676 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Tested boards</span><br><span style="color: hsl(120, 100%, 40%);">+-------------</span><br><span style="color: hsl(120, 100%, 40%);">+The following boards were tested for this release:</span><br><span style="color: hsl(120, 100%, 40%);">+* asrock/e350m1 4.4-1890</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kfsn4-dre 4.4-1698 / 4.5-17</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/kgpe-d16 4.4-1802 / 4.5-17</span><br><span style="color: hsl(120, 100%, 40%);">+* emulation/qemu-q35 4.4-1698 / 4.5-8</span><br><span style="color: hsl(120, 100%, 40%);">+* gigabyte/ga-b75m-d3v 4.4-1757</span><br><span style="color: hsl(120, 100%, 40%);">+* google/peppy 4.4-1882</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/g505s 4.4-1739</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/x201 4.4-1886</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/x220 4.4-1746 / 4.5-17</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot statistics</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Commits: 1889</span><br><span style="color: hsl(120, 100%, 40%);">+* Average Commits per day: 10.92</span><br><span style="color: hsl(120, 100%, 40%);">+* Total authors: 119</span><br><span style="color: hsl(120, 100%, 40%);">+* New authors: 47</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Reviewers: 67</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Submitters: 19</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines added: 164950</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines removed: -182737</span><br><span style="color: hsl(120, 100%, 40%);">+* Total difference: -17787</span><br><span>diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..f6c29c6</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.6-relnotes.md</span><br><span>@@ -0,0 +1,486 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Announcing coreboot 4.6</span><br><span style="color: hsl(120, 100%, 40%);">+=======================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+We are happy to announce the April 2017 release of coreboot, version</span><br><span style="color: hsl(120, 100%, 40%);">+4.6.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The 4.6 release covers commit e74f5eaa to commit db508565</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Since the last release in October 2016, the coreboot project had 1708</span><br><span style="color: hsl(120, 100%, 40%);">+commits by 121 authors. The release tarballs and gpg signatures are</span><br><span style="color: hsl(120, 100%, 40%);">+available in the usual place at https://www.coreboot.org/downloads</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There is a pgp signed 4.6 tag in the git repository, and a branch will</span><br><span style="color: hsl(120, 100%, 40%);">+be created as needed.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Changes: Past, ongoing, and future</span><br><span style="color: hsl(120, 100%, 40%);">+----------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### CBMEM console development and the Linux Kernel</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Our cbmem debug console was updated with some nice features. The cbmem</span><br><span style="color: hsl(120, 100%, 40%);">+console now persists between reboots and is able to be used on some</span><br><span style="color: hsl(120, 100%, 40%);">+platforms via late init. Also there is a new Linux kernel driver which</span><br><span style="color: hsl(120, 100%, 40%);">+removes the need for the old cbmem tool to read from the cbmem area. You</span><br><span style="color: hsl(120, 100%, 40%);">+can find the patch here https://patchwork.kernel.org/patch/9641997/ and</span><br><span style="color: hsl(120, 100%, 40%);">+it can be enabled via GOOGLE_MEMCONSOLE_COREBOOT kconfig option in your</span><br><span style="color: hsl(120, 100%, 40%);">+kernel - Note that this name may change going forward.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Critical bugs in TPM 1.2 support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot currently has issues with the TPM 1.2 LPC driver</span><br><span style="color: hsl(120, 100%, 40%);">+implementation. This leads to a misbehavior in SeaBIOS where the TPM</span><br><span style="color: hsl(120, 100%, 40%);">+gets temporarily deactivated. We plan to publish the bugfix release</span><br><span style="color: hsl(120, 100%, 40%);">+4.6.1 when we have these issues sorted out.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Native graphics and ram init improvements</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The native graphics was reworked a while ago and should finally support</span><br><span style="color: hsl(120, 100%, 40%);">+Windows. Numerous bug fixes and EDID support is also now available.</span><br><span style="color: hsl(120, 100%, 40%);">+Finally, the native ram initialization for sandybridge/ivybridge</span><br><span style="color: hsl(120, 100%, 40%);">+platforms got patched and supports more RAM modules.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### New and fresh payloads</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SeaBIOS, FiLO, and iPXE were all recently updated to the latest</span><br><span style="color: hsl(120, 100%, 40%);">+versions. Https downloads are the default for all payloads now. We</span><br><span style="color: hsl(120, 100%, 40%);">+provide the libpayload project which is used for writing own payloads</span><br><span style="color: hsl(120, 100%, 40%);">+from scratch. The library is MOSTLY licensed under BSD and recently</span><br><span style="color: hsl(120, 100%, 40%);">+received new functionality in order to prepare for the upcoming</span><br><span style="color: hsl(120, 100%, 40%);">+replacement for the old nvramcui payload. This new payload is called</span><br><span style="color: hsl(120, 100%, 40%);">+cbui and is based on the nuklear graphics library including keyboard and</span><br><span style="color: hsl(120, 100%, 40%);">+mouse support. The cbui payload is currently expected to be merged into</span><br><span style="color: hsl(120, 100%, 40%);">+the main coreboot tree before the next release. The upstream repository</span><br><span style="color: hsl(120, 100%, 40%);">+is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### UEFI support: A long road to go</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot can be used with the Tianocore EDK2 UEFI implementation which</span><br><span style="color: hsl(120, 100%, 40%);">+is open source and available at Github. Sadly it is not currently</span><br><span style="color: hsl(120, 100%, 40%);">+integrated into the coreboot build. This has several reasons:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.</span><br><span style="color: hsl(120, 100%, 40%);">+* Incompatibilities with code inside the EDK2 which has not been updated.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+We started to make progress with the integration into our sources and</span><br><span style="color: hsl(120, 100%, 40%);">+the hope is that by the end of the summer, we finally support the EDK2</span><br><span style="color: hsl(120, 100%, 40%);">+payload out-of-the- box. See the current patch state at</span><br><span style="color: hsl(120, 100%, 40%);">+http://review.coreboot.org/#/c/15057/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Fighting blobs and proprietary HW components</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot's ultimate goal would be to replace any closed source firmware</span><br><span style="color: hsl(120, 100%, 40%);">+stack with free software components. Unfortunately this is not always</span><br><span style="color: hsl(120, 100%, 40%);">+possible due to signed binaries such as the Intel ME firmware, the AMD</span><br><span style="color: hsl(120, 100%, 40%);">+PSP and microcode. Recently, a way was discovered to let the Intel ME</span><br><span style="color: hsl(120, 100%, 40%);">+run in a functional error state and reduce it from 1.5/5MB to 80KB. It's</span><br><span style="color: hsl(120, 100%, 40%);">+not perfect but it works from Nehalem up to Skylake based Intel systems.</span><br><span style="color: hsl(120, 100%, 40%);">+The tool is now integrated into the coreboot build system. The upstream</span><br><span style="color: hsl(120, 100%, 40%);">+repository is https://github.com/corna/me_cleaner</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Another ongoing improvement is the new utility blobtool. It is currently</span><br><span style="color: hsl(120, 100%, 40%);">+used for generating the flash descriptor and GbE configuration data on</span><br><span style="color: hsl(120, 100%, 40%);">+older mainboard which are known to be free software. It can easily be</span><br><span style="color: hsl(120, 100%, 40%);">+extended for different binaries with well-defined specifications.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Did you say Ada?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot now supports Ada, and a lot work was done integrating Ada into</span><br><span style="color: hsl(120, 100%, 40%);">+our toolchain. At the moment only the support for formal verification is</span><br><span style="color: hsl(120, 100%, 40%);">+missing and will be soon added. At that point, we can prove the absence</span><br><span style="color: hsl(120, 100%, 40%);">+of runtime errors in our Ada code. In short, everybody can start</span><br><span style="color: hsl(120, 100%, 40%);">+developing Ada code for our project.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The existing Ada code which can be used from now on is another native</span><br><span style="color: hsl(120, 100%, 40%);">+graphics initialization which will replace in the long term the current</span><br><span style="color: hsl(120, 100%, 40%);">+implementation. The native graphics code supports all Intel platforms up</span><br><span style="color: hsl(120, 100%, 40%);">+to skylake. We offer support for HDMI, VGA, DVI and DP external</span><br><span style="color: hsl(120, 100%, 40%);">+interfaces as well and is ready to be integrated into our mainboard</span><br><span style="color: hsl(120, 100%, 40%);">+implementations.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Toolchain updates</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+A new coreboot toolchain is out. The major toolchain change was going</span><br><span style="color: hsl(120, 100%, 40%);">+from GCC version 5.3.0 to 6.3.0. There were also minor version updates</span><br><span style="color: hsl(120, 100%, 40%);">+to GMP, MPFR, Binutils, GDB, IASL, and Clang.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Deprecation policy for boards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Starting with this release there will be a policy for deprecating</span><br><span style="color: hsl(120, 100%, 40%);">+unmaintained boards. See the end of this announcement for details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Change Summary</span><br><span style="color: hsl(120, 100%, 40%);">+--------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Build system (20 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Clean up Kconfig</span><br><span style="color: hsl(120, 100%, 40%);">+* Show more useful error messages</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Codebase cleanup (94 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Many fixes for files to pass checkpatch. Lots more to do here.</span><br><span style="color: hsl(120, 100%, 40%);">+* Remove commented out code</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates to transition away from device_t</span><br><span style="color: hsl(120, 100%, 40%);">+* Work to get rid of included C files</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Documentation (6 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Start adding technotes/Design docs</span><br><span style="color: hsl(120, 100%, 40%);">+* Add Kconfig documentation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ACPI & acpigen library</span><br><span style="color: hsl(120, 100%, 40%);">+* Add GPIO macros</span><br><span style="color: hsl(120, 100%, 40%);">+* Clean up and add more functions to ACPIGEN library</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+EC (26 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add roda/it8518 embedded controller</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+TPM (41 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Cleanup</span><br><span style="color: hsl(120, 100%, 40%);">+* Update ACPI ASL, Runtime generate ACPI table for TPM driver</span><br><span style="color: hsl(120, 100%, 40%);">+* Make SPI TPM driver CAR-safe</span><br><span style="color: hsl(120, 100%, 40%);">+* Update TPM init sequence</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Devices (24 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add a new SPI device type</span><br><span style="color: hsl(120, 100%, 40%);">+* Allow devicetree accesses in postcar stage</span><br><span style="color: hsl(120, 100%, 40%);">+* PCIEXP_ASPM: Unify code with other PCI-e tuning</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Lib (28 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add option to use Ada code in ramstage</span><br><span style="color: hsl(120, 100%, 40%);">+* bootstate: add arch specific hook at coreboot exit</span><br><span style="color: hsl(120, 100%, 40%);">+* cbfs: Add API to locate a file from specific region</span><br><span style="color: hsl(120, 100%, 40%);">+* Add library to handle SPD data in CBFS or DIMM</span><br><span style="color: hsl(120, 100%, 40%);">+* Add region file support</span><br><span style="color: hsl(120, 100%, 40%);">+* Turn CBMEM console into a ring buffer that can persist across reboots</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Commonlib (11 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add xmalloc, xzmalloc and dma routines</span><br><span style="color: hsl(120, 100%, 40%);">+* Add input and output buffer helpers</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Drivers (29 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c: Pass in i2c_generic_config into i2c_generic_fill_ssdt</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c/alps: Add support for ALPS Touchpad driver</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c/generic: Add support for GPIO IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c/generic: Enable support for adding PowerResource for device</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c/hid: Add generic I2C HID driver</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c/max98927: add i2c driver for Maxim 98927 codec</span><br><span style="color: hsl(120, 100%, 40%);">+* i2c/wacom_ts: Add support for WCOM touchscreen device driver</span><br><span style="color: hsl(120, 100%, 40%);">+* pc80/rtc: Check cmos checksum BEFORE reading cmos value</span><br><span style="color: hsl(120, 100%, 40%);">+* regulator: Add driver for handling GPIO-based fixed regulator</span><br><span style="color: hsl(120, 100%, 40%);">+* storage: Add SD/MMC/eMMC driver based upon depthcharge</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPI interface</span><br><span style="color: hsl(120, 100%, 40%);">+* Significant cleanup and refactoring</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Include (17 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/intel: Add MSR to support enabling turbo frequency</span><br><span style="color: hsl(120, 100%, 40%);">+* elog: Add all EC event codes</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SuperIO (12 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates for ITE SIOs</span><br><span style="color: hsl(120, 100%, 40%);">+* Add 2 new chips</span><br><span style="color: hsl(120, 100%, 40%);">+* Consolidate code to use common routines</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Vboot (23 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for recovery hash space in TPM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+RISC-V (25 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add lowRISC System On Chip support</span><br><span style="color: hsl(120, 100%, 40%);">+* Cbmem patches, move to common architectural code</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ARM (16 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Init new serial struct variables for samsung exynos5420 & allwinner</span><br><span style="color: hsl(120, 100%, 40%);">+ a10</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix verstage to use proper assembly versions of mem*()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+RockChip RK3399 & platforms (46 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Memory, I2C, USB, SD & Display fixes</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+X86 Intel (193 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and</span><br><span style="color: hsl(120, 100%, 40%);">+ 3.</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/intel/common: Add/Use common function to set virtualization</span><br><span style="color: hsl(120, 100%, 40%);">+* drivers/intel/fsp1_1: Fix boot failure for non-verstage case</span><br><span style="color: hsl(120, 100%, 40%);">+* drivers/intel/fsp2_0: Reset on invalid stage cache.</span><br><span style="color: hsl(120, 100%, 40%);">+* drivers/intel/gma: Add textmode using libgfxinit & use scaling to</span><br><span style="color: hsl(120, 100%, 40%);">+ simplify config</span><br><span style="color: hsl(120, 100%, 40%);">+* drivers/intel/mipi_camera: Add MIPI CSI camera SSDT generator</span><br><span style="color: hsl(120, 100%, 40%);">+* broadwell_de: Add SMM code</span><br><span style="color: hsl(120, 100%, 40%);">+* intelblocks/msr: Move intel x86 MSR definition into common location</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/broadwell: Use the correct SATA port config for setting IOBP</span><br><span style="color: hsl(120, 100%, 40%);">+ register</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/wifi: Create ACPI objects for wifi SAR configuration</span><br><span style="color: hsl(120, 100%, 40%);">+* lynxpoint bd82x6x: Enable PCI-to-PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* mrc: Add support for separate training cache in recovery mode</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual</span><br><span style="color: hsl(120, 100%, 40%);">+ Channel</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/i945/raminit: Add fixes for 800MHz & 1067MHz FSB CPUs</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/intel/gm45: Fix panel-power-sequence clock divisor</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/intel/i945: Fix PEG port on 945gc & sdram_enhanced_addressing for</span><br><span style="color: hsl(120, 100%, 40%);">+ channel1</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/intel/pineview: Move to early cbmem</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/pineview/raminit: Skip Jedec init on resume, fix hot reset path</span><br><span style="color: hsl(120, 100%, 40%);">+* nb/intel/sandybridge/gma: Always initialize DP buffer translation</span><br><span style="color: hsl(120, 100%, 40%);">+* sb/ich7: Use common/gpio.h to set up GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+* sb/intel/bd82x6x: Add TCO_Lock in finalize step</span><br><span style="color: hsl(120, 100%, 40%);">+* sb/intel/common/gpio: Support ICH9M and prior</span><br><span style="color: hsl(120, 100%, 40%);">+* sb/intel/i82801gx: Add i2c_block_read to smbus.h</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+sandybridge/raminit</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix CAS Write Latency, disable_channel, normalize_training & odt stretch</span><br><span style="color: hsl(120, 100%, 40%);">+* Separate Sandybridge and Ivybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Reset internal state on fallback attempts</span><br><span style="color: hsl(120, 100%, 40%);">+* Find CMD rate per channel</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+soc/intel/common</span><br><span style="color: hsl(120, 100%, 40%);">+* Add common routines for HECI, ITSS, PCR, RTC, systemagent, UART, XHCI,</span><br><span style="color: hsl(120, 100%, 40%);">+& LPSS</span><br><span style="color: hsl(120, 100%, 40%);">+* Save Memory DIMM Information in SMBIOS table</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Apollolake (183 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Switch to common routines for LPSS, RTC, ITSS, UART, XHCI, & PCR</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable turbo</span><br><span style="color: hsl(120, 100%, 40%);">+* Add save/restore variable MRC cache</span><br><span style="color: hsl(120, 100%, 40%);">+* Allow ApolloLake SoC to use FSP CAR Init</span><br><span style="color: hsl(120, 100%, 40%);">+* Allow USB2 eye pattern configuration in devicetree</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Quark & platforms (14 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix I2c & Serial port config</span><br><span style="color: hsl(120, 100%, 40%);">+* Add vboot support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ga-g41m-es2l, x4x northbridge & LGA775 (23 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Memory fixes</span><br><span style="color: hsl(120, 100%, 40%);">+* Add S3 suspend/resume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Skylake / Kabylake (208 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Add devicetree settings for acoustic noise mitigation</span><br><span style="color: hsl(120, 100%, 40%);">+* Perform CPU MP Init before FSP-S Init</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for GSPI controller & add GSPI controller get_config</span><br><span style="color: hsl(120, 100%, 40%);">+support</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable Systemagent IMGU</span><br><span style="color: hsl(120, 100%, 40%);">+* Add USB Port Over Current support & Expand USB OC pins support PCH-H</span><br><span style="color: hsl(120, 100%, 40%);">+* Extract DIMM Information from FSP MEM INFO HOB</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for eSPI SMI events</span><br><span style="color: hsl(120, 100%, 40%);">+* Update ACPI & various methods</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+X86 amd (116 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* ACPI S3: Remove HIGH_MEMORY_SAVE where possible</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain</span><br><span style="color: hsl(120, 100%, 40%);">+* binaryPI platforms: Drop ACPI S3 support</span><br><span style="color: hsl(120, 100%, 40%);">+* sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used</span><br><span style="color: hsl(120, 100%, 40%);">+* southbridge/amd: Add LPC bridge acpi path for Family14 and SB800</span><br><span style="color: hsl(120, 100%, 40%);">+* arch/x86: remove CAR global migration when postcar stage is used</span><br><span style="color: hsl(120, 100%, 40%);">+* x86/acpi: Add VFCT table</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AMD: vendorcode, AGESA, binaryPI (72 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Cleanup & consolidate duplicate code</span><br><span style="color: hsl(120, 100%, 40%);">+* Fork for new cache-as-ram init code & Fix binaryPI cache-as-ram</span><br><span style="color: hsl(120, 100%, 40%);">+* Refactor S3 support functions and Delay ACPI S3 backup until ramstage</span><br><span style="color: hsl(120, 100%, 40%);">+ loader</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+amd/mct:</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix CsMux45 configuration, maximum read latency, & DQ mask calculation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Mainboards (198 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* asus/f2a85-m_le: Activate IOMMU support</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/h8: Add USB Always On</span><br><span style="color: hsl(120, 100%, 40%);">+* google/oak: Enable dual DSI for rowan and the BOE 8-lane MIPI/DSI panel</span><br><span style="color: hsl(120, 100%, 40%);">+* google/parrot: Fix keyboard interrupts, DSDT</span><br><span style="color: hsl(120, 100%, 40%);">+* google/veyron: Work around RAM code strapping error</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/t400: Rewrite dock from t60</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/d510mo: enable ACPI resume from S3</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/d945gclf: Fix resume from S3 suspend</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/t400: Implement hybrid graphic in romstage</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable libgfxinit on lenovo/t420 & x230, kontron/ktqm77, google/slippy</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo/x60,t60: Move EC CMOS parameters in checksummed space</span><br><span style="color: hsl(120, 100%, 40%);">+* mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing</span><br><span style="color: hsl(120, 100%, 40%);">+* mc_tcu3: Swap LVDS even and odd lanes for a certain hardware</span><br><span style="color: hsl(120, 100%, 40%);">+* purism/librem13: Enable support for M.2 NVMe & Fix M.2 issues</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Payloads (53 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Update FILO, SeaBIOS, & iPXE versions</span><br><span style="color: hsl(120, 100%, 40%);">+* Many libpayload fixes and updates</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Toolchain (19 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Utilities: (145 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* abuild: Build saved config files and print failed builds at the end</span><br><span style="color: hsl(120, 100%, 40%);">+* autoport: Create superiotool logs and fix romstage generator</span><br><span style="color: hsl(120, 100%, 40%);">+* board-status: Update bucketize script and add README file</span><br><span style="color: hsl(120, 100%, 40%);">+* cbfstool: Add cbfs-compression-tool and enable adding precompressed</span><br><span style="color: hsl(120, 100%, 40%);">+ files</span><br><span style="color: hsl(120, 100%, 40%);">+* cbmem: Add custom aligned memcpy() implementation</span><br><span style="color: hsl(120, 100%, 40%);">+* ectool: Fix timeout on sending EC command and support OpenBSD</span><br><span style="color: hsl(120, 100%, 40%);">+* ifdtool: Fix ICH Gbe unlock</span><br><span style="color: hsl(120, 100%, 40%);">+* intelmetool: Add support for Wildcat Point LP, fix segfault on edge</span><br><span style="color: hsl(120, 100%, 40%);">+ cases</span><br><span style="color: hsl(120, 100%, 40%);">+* inteltool: Add support for CH6-10, ICH10, Wildcat Point-LP and fix ICH</span><br><span style="color: hsl(120, 100%, 40%);">+SPIBAR</span><br><span style="color: hsl(120, 100%, 40%);">+* sconfig: Add a new SPI device type</span><br><span style="color: hsl(120, 100%, 40%);">+* superiotool: Add new chips - IT8783E/F, W83627DHG, W83627EHG, F71808A</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Changes in chips</span><br><span style="color: hsl(120, 100%, 40%);">+----------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 1 processor & northbridge:</span><br><span style="color: hsl(120, 100%, 40%);">+* amd/pi/00670F00</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 1 soc:</span><br><span style="color: hsl(120, 100%, 40%);">+* lowrisc/lowrisc</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Removed 1 northbridge:</span><br><span style="color: hsl(120, 100%, 40%);">+* intel/e7501</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 2 sios:</span><br><span style="color: hsl(120, 100%, 40%);">+* fintek/f71808a</span><br><span style="color: hsl(120, 100%, 40%);">+* ite/it8783ef</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Mainboard changes</span><br><span style="color: hsl(120, 100%, 40%);">+-----------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 52 mainboards and variants:</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD Gardenia - AMD Stoney Ridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus F2A85_M_PRO - AMD Family 15h Trinity</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus P5GC_MX - Intel Socket LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+* Gigabyte GA_945GCM_S2L & GA_945GCM_S2C variant - Intel Socket LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Auron variants: Yuna, Gandof, Lulu - Intel Broadwell</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Beltino variants: McCloud, Monroe, Tricky, Zako - Intel Haswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Eve - Intel Kabylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Fizz - Intel Kabylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Gru variants: Bob, Scarlet - RockChip RK3399</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Oak variants: Hana, Rowan - MediaTek MT8173</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Poppy & Soraka variant - Intel Kabylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Rambi variants: Banjo, Candy, Clapper, Glimmer, Gnawty, Heli,</span><br><span style="color: hsl(120, 100%, 40%);">+ Kip, Orco, Quawks, Squawks, Sumo, Swanky, & Winky - Intel Baytrail</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Reef variants: Sand, Snappy, Nasher - Intel Apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Slippy variants: Leon, Wolf - Intel Haswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel KBLRVP3 & KBLRVP7 - Intel Kabylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel LEAFHILL - Intel Apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel MINNOW3 - Intel Apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo L520: Intel Sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo S230U: Intel Ivybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo X1 Carbon GEN1 - Intel Sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* lowRISC NEXYS4DDR - RiscV</span><br><span style="color: hsl(120, 100%, 40%);">+* MSI MS7721 - AMD Bulldozer</span><br><span style="color: hsl(120, 100%, 40%);">+* PC Engines APU2 - AMD Jaguar</span><br><span style="color: hsl(120, 100%, 40%);">+* RODA RV11 & RW11 variant - Intel Ivybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Sapphire Pure Platinum H61 - Intel Socket LGA1155</span><br><span style="color: hsl(120, 100%, 40%);">+* Siemens MC_APL1 - Intel Apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Removed 10 mainboard variants:</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Auron (Still available as a base-board for variants)</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Veyron Chromeboxes: Brain, Danger, Emile, Romy</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Veyron Test Projects: Gus, Nicky, Pinky, Shark, Thea</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Utilities</span><br><span style="color: hsl(120, 100%, 40%);">+---------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 2 new utilities:</span><br><span style="color: hsl(120, 100%, 40%);">+* blobtool</span><br><span style="color: hsl(120, 100%, 40%);">+* me_cleaner</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Submodules</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Updated 5 submodules</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/blobs (10 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/arm-trusted-firmware (172 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/vboot (158 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* 3rdparty/chromeec/ (810 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+* util/nvidia/cbootimage (2 commits)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Tested boards</span><br><span style="color: hsl(120, 100%, 40%);">+-------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The following boards were tested recently:</span><br><span style="color: hsl(120, 100%, 40%);">+* emulation qemu-q35 4.6-1</span><br><span style="color: hsl(120, 100%, 40%);">+* asus kgpe-d16 4.6-1</span><br><span style="color: hsl(120, 100%, 40%);">+* asus kfsn4-dre 4.6-1</span><br><span style="color: hsl(120, 100%, 40%);">+* asus p5gc-mx 4.6-1</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo x60 4.5-1681 / 4.6-7</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo x230 4.5-1674 / 4.6-27</span><br><span style="color: hsl(120, 100%, 40%);">+* asrock e350m1 4.5-1662 / 4.6-7</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo t420 4.5-1640</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo x200 4.5-1598 / 4.6-33</span><br><span style="color: hsl(120, 100%, 40%);">+* sapphire pureplatinumh61 4.5-1575</span><br><span style="color: hsl(120, 100%, 40%);">+* gigabyte ga-945gcm-s2l 4.5-1568</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo t400 4.5-1564</span><br><span style="color: hsl(120, 100%, 40%);">+* lenovo t60 4.5-1559</span><br><span style="color: hsl(120, 100%, 40%);">+* gigabyte m57sli 4.5-1526</span><br><span style="color: hsl(120, 100%, 40%);">+* purism librem13 4.5-1503</span><br><span style="color: hsl(120, 100%, 40%);">+* gigabyte ga-g41m-es2l 4.5-1444</span><br><span style="color: hsl(120, 100%, 40%);">+* google slippy 4.5-1441</span><br><span style="color: hsl(120, 100%, 40%);">+* intel d510mo 4.5-1341</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot statistics from e74f5eaa43 to db508565d2</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Commits: 1708</span><br><span style="color: hsl(120, 100%, 40%);">+* Average Commits per day: 8.75</span><br><span style="color: hsl(120, 100%, 40%);">+* Total authors: 121</span><br><span style="color: hsl(120, 100%, 40%);">+* New authors: 34</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Reviewers: 72</span><br><span style="color: hsl(120, 100%, 40%);">+* Total Submitters: 19</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines added: 177576</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines removed: - 107460</span><br><span style="color: hsl(120, 100%, 40%);">+* Total difference: 70116</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Code removal after the 4.6 release</span><br><span style="color: hsl(120, 100%, 40%);">+----------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The only platform currently scheduled for removal is the</span><br><span style="color: hsl(120, 100%, 40%);">+bifferos/bifferboard & soc/rdc/r8610. This platform is one of two that</span><br><span style="color: hsl(120, 100%, 40%);">+still uses romcc to compile romstage and doesn't have cache-as-ram in</span><br><span style="color: hsl(120, 100%, 40%);">+romstage - the others were all removed long ago. Additionally, it seems</span><br><span style="color: hsl(120, 100%, 40%);">+to be impossible to buy, so as far as it can be determined, no testing</span><br><span style="color: hsl(120, 100%, 40%);">+has been done recently.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Code removal after the 4.7 release</span><br><span style="color: hsl(120, 100%, 40%);">+----------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+One of the things that the coreboot project has struggled with is how to</span><br><span style="color: hsl(120, 100%, 40%);">+maintain the older platforms while still moving the rest of the</span><br><span style="color: hsl(120, 100%, 40%);">+platforms forward. Currently there are numerous platforms in the</span><br><span style="color: hsl(120, 100%, 40%);">+codebase which have not been well maintained.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Starting with the 4.7 release in October, the coreboot leadership is</span><br><span style="color: hsl(120, 100%, 40%);">+going to set standards that platforms are expected to meet to remain in</span><br><span style="color: hsl(120, 100%, 40%);">+the active codebase. These will generally be announced 3 - 6 months in</span><br><span style="color: hsl(120, 100%, 40%);">+advance to give time to get changes in. The expectation is not</span><br><span style="color: hsl(120, 100%, 40%);">+necessarily even that all work to meet the goal will be completed, but</span><br><span style="color: hsl(120, 100%, 40%);">+it is expected that a reasonable effort has started to meet the goal at</span><br><span style="color: hsl(120, 100%, 40%);">+the time of the release. Regardless of the work that's been done,</span><br><span style="color: hsl(120, 100%, 40%);">+platforms which have not met the goal by the following release will be</span><br><span style="color: hsl(120, 100%, 40%);">+removed.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The next expectation that will need to be met for all platforms is cbmem</span><br><span style="color: hsl(120, 100%, 40%);">+in romstage. This currently affects numerous platforms, including most,</span><br><span style="color: hsl(120, 100%, 40%);">+if not all of AMD's platforms. Work to update many of these platforms</span><br><span style="color: hsl(120, 100%, 40%);">+has started, but there are others that have not made any progress</span><br><span style="color: hsl(120, 100%, 40%);">+towards this goal. A list of the platforms that are affected by this</span><br><span style="color: hsl(120, 100%, 40%);">+will be sent to the mailing list shortly.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Code removal after the 4.8 release</span><br><span style="color: hsl(120, 100%, 40%);">+----------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+To further clean things up, starting with the 4.8 release, any platform</span><br><span style="color: hsl(120, 100%, 40%);">+that does not have a successful boot logged in the board_status repo in</span><br><span style="color: hsl(120, 100%, 40%);">+the previous year (that is, within the previous two releases) will be</span><br><span style="color: hsl(120, 100%, 40%);">+removed from the maintained coreboot codebase. Chips that do not have</span><br><span style="color: hsl(120, 100%, 40%);">+any associated boards will also be removed. These platforms will be</span><br><span style="color: hsl(120, 100%, 40%);">+announced before the release so that there is time for people to test if</span><br><span style="color: hsl(120, 100%, 40%);">+desired.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This is not meant to be a high bar, but as a measure to clean up the</span><br><span style="color: hsl(120, 100%, 40%);">+codebase and eliminate boards and chips that are actually no longer</span><br><span style="color: hsl(120, 100%, 40%);">+being used. The cleanup will happen just after the release, so the</span><br><span style="color: hsl(120, 100%, 40%);">+removed platforms will still be available in the release branch if</span><br><span style="color: hsl(120, 100%, 40%);">+desired. If there is still interest, developers can bring back old chips</span><br><span style="color: hsl(120, 100%, 40%);">+and boards by porting them to the new tree (and bringing them to current</span><br><span style="color: hsl(120, 100%, 40%);">+standards).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This gives everyone until April 2018 to get any boards that they care</span><br><span style="color: hsl(120, 100%, 40%);">+about tested before the first removal.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+All the code removal information will also be sent to the mailing list</span><br><span style="color: hsl(120, 100%, 40%);">+along with additional details.</span><br><span>diff --git a/Documentation/releases/coreboot-4.7-relnotes.md b/Documentation/releases/coreboot-4.7-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..ac9d817</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.7-relnotes.md</span><br><span>@@ -0,0 +1,197 @@</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot 4.7 release notes</span><br><span style="color: hsl(120, 100%, 40%);">+==========================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The 4.7 release covers commit 0a4a4f7ae4 to commit fd470f7163</span><br><span style="color: hsl(120, 100%, 40%);">+Since the last release in April 2017, the coreboot project had 2573 commits by 150 authors.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There is a pgp signed 4.7 tag in the git repository, and a branch will be created as needed.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+New chipsets</span><br><span style="color: hsl(120, 100%, 40%);">+------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD Stoney Ridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel i82801jx Southbridge (ICH10)</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel Denverton and Denverton-NS</span><br><span style="color: hsl(120, 100%, 40%);">+* Work has started on Intel Cannon Lake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 47 mainboards & variants:</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Acer Chromebook 14 CB3-431 [google/edgar] Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Acer Chromebook 15 CB3-532 [google/banon] Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Acer Chromebook N7 C731 [google/relm] Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* ASRock B75 Pro3-M Intel Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* ASRock G41C-GS R2.0 Intel G41/ICH7</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus AM1I-A AMD Kabini</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus Chromebook C202SA/C300SA/C301SA (google/terra) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Biostar A68N-5200 AMD Kabini</span><br><span style="color: hsl(120, 100%, 40%);">+* Compulab Intense-PC Intel Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Dell Chromebook 11 3180/3189 (google/kefka) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Foxconn G41S-K Intel G41/ICH7</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Coral Intel Apollo Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Grunt AMD Stoney Ridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Kahlee AMD Stoney Ridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Meowth Intel Cannon Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Nami Intel Kaby Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Nautilus Intel Kaby Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Nefario Rockchip RK3399</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Rainier Rockchip RK3399</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Soraka Intel Kaby Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Zoombini Intel Cannon Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* HP Chromebook 11 G5 (google/setzer) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* HP EliteBook 2570p Intel Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* HP EliteBook 2760p Intel Sandy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* HP EliteBook 8460p Intel Sandy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* HP EliteBook 8470p Intel Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* HP EliteBook Revolve 810 G1 Intel Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel Cannnlake RVPU Intel Cannon Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel Cannonlake RVPY Intel Cannon Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel D410PT Intel Atom D410</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel DG43GT Intel G43/ICH10</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel GLKRVP Intel Gemini Lake</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel Harcuvar Intel Denverton</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel NUC DCP847SKE Intel Sandy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel Saddle Brook reference board Intel Skylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo N22/N42 Chromebook (google/reks) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo T430 Intel Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo Thinkpad 11e/Yoga Chromebook G3</span><br><span style="color: hsl(120, 100%, 40%);">+ (google/ultima) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo ThinkPad X131e Intel Sandy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo Z61T Intel i945/ICH7</span><br><span style="color: hsl(120, 100%, 40%);">+* PC Engines APU3 AMD Steppe Eagle</span><br><span style="color: hsl(120, 100%, 40%);">+* PC Engines APU4 AMD Steppe Eagle</span><br><span style="color: hsl(120, 100%, 40%);">+* PC Engines APU5 AMD Steppe Eagle</span><br><span style="color: hsl(120, 100%, 40%);">+* Purism Librem 13 v2 Intel Skylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Purism Librem 15 v3 Intel Skylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Samsung Chromebook 3 (google/celes) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* White label Chromebook (google/wizpig) Intel Braswell</span><br><span style="color: hsl(120, 100%, 40%);">+* WinNET G170 VIA CN700</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Removed 2 mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+--------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Biferos Bifferboard</span><br><span style="color: hsl(120, 100%, 40%);">+* Google Cosmos</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+New Embedded Controller</span><br><span style="color: hsl(120, 100%, 40%);">+-----------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* KBC1126 used in HP EliteBooks</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+General changes</span><br><span style="color: hsl(120, 100%, 40%);">+---------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Integrate me_cleaner</span><br><span style="color: hsl(120, 100%, 40%);">+* Add flashconsole implementation</span><br><span style="color: hsl(120, 100%, 40%);">+* Build Tianocore UEFI payload from upstream source</span><br><span style="color: hsl(120, 100%, 40%);">+* Remove CMOS NVRAM configurable baud rates</span><br><span style="color: hsl(120, 100%, 40%);">+* A common mrc_cache driver to store romstage settings in SPI flash</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Google ChromeOS devices:</span><br><span style="color: hsl(120, 100%, 40%);">+------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Add ACPI USB port definitions for many boards</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix preprocessor guards for LPC TPM</span><br><span style="color: hsl(120, 100%, 40%);">+* Remove non-existent IRQ for LPC TPM</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix LED control for mccloud</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable keyboard backlight at boot on equipped boards</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix ACPI data for non-google EC's to improve Windows compatibility</span><br><span style="color: hsl(120, 100%, 40%);">+* Add missing SPD files for chell, fixing support for > 4GB boards</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Lenovo Thinkpads:</span><br><span style="color: hsl(120, 100%, 40%);">+-----------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for passive cooling</span><br><span style="color: hsl(120, 100%, 40%);">+* Add ACPI fan control</span><br><span style="color: hsl(120, 100%, 40%);">+* Add BDC detection and power saving</span><br><span style="color: hsl(120, 100%, 40%);">+* Unify hybrid graphics and improved power saving</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel Braswell:</span><br><span style="color: hsl(120, 100%, 40%);">+---------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for all outstanding Braswell ChromeOS devices</span><br><span style="color: hsl(120, 100%, 40%);">+* Update FSP 1.1 header to v1.1.7.0</span><br><span style="color: hsl(120, 100%, 40%);">+* Adjust FSP header revision check to be less stringent</span><br><span style="color: hsl(120, 100%, 40%);">+* Upstream numerous commits from Chromium tree</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix ACPI scope for I2C devices</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix SPI write after flash lockdown set</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Legacy Intel Boards:</span><br><span style="color: hsl(120, 100%, 40%);">+--------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Unify Intel VBT handling</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for loading external VBT</span><br><span style="color: hsl(120, 100%, 40%);">+* Provide the VBT through Intel OpRegion method on all platforms</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix low memory corruption on S3 resume path</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel Sandy Bridge:</span><br><span style="color: hsl(120, 100%, 40%);">+------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Add a Kconfig option to ignore XMP max DIMMs</span><br><span style="color: hsl(120, 100%, 40%);">+* Add Kconfig option for max. DRAM frequency fuses</span><br><span style="color: hsl(120, 100%, 40%);">+* Advertise correct DRAM frequency on Ivy Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Improve CAS/frequency selection</span><br><span style="color: hsl(120, 100%, 40%);">+* Use command rate 2T on channels with two DIMMs installed for improved</span><br><span style="color: hsl(120, 100%, 40%);">+stability</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel X4X:</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix booting with FSB800 DDR667 combination</span><br><span style="color: hsl(120, 100%, 40%);">+* Rework ram DQS receiver enable training sequence</span><br><span style="color: hsl(120, 100%, 40%);">+* Rework and fix SPD reading and decoding</span><br><span style="color: hsl(120, 100%, 40%);">+* Allow external GPU to take VGA cycles</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel GM45:</span><br><span style="color: hsl(120, 100%, 40%);">+-----------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Improve compatibility with mixed DIMMs</span><br><span style="color: hsl(120, 100%, 40%);">+* Add romstage timings</span><br><span style="color: hsl(120, 100%, 40%);">+* Set the display backlight PWM correctly</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel Pineview:</span><br><span style="color: hsl(120, 100%, 40%);">+---------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Enable remapping of memory to allow for 4G or more memory</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel I440BX</span><br><span style="color: hsl(120, 100%, 40%);">+------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Implement early CBMEM support</span><br><span style="color: hsl(120, 100%, 40%);">+* Fix RAM init programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AMD AGESA</span><br><span style="color: hsl(120, 100%, 40%);">+---------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Move boards to early CBMEM and add timestamps</span><br><span style="color: hsl(120, 100%, 40%);">+* Refactor boards away from using agesawrapper</span><br><span style="color: hsl(120, 100%, 40%);">+* Wipe unused sources under vendorcode</span><br><span style="color: hsl(120, 100%, 40%);">+* Re-enable ACPI S3 after fixing low memory corruptions</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AMD binaryPI</span><br><span style="color: hsl(120, 100%, 40%);">+------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Move boards to early CBMEM</span><br><span style="color: hsl(120, 100%, 40%);">+* Continue work on cleaning up headers</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+libgfxinit</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Support new hardware: Broxton/APL (DP and HDMI only), Skylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Handle framebuffer mapping in the library</span><br><span style="color: hsl(120, 100%, 40%);">+* Make DP training more compatible and tolerant</span><br><span style="color: hsl(120, 100%, 40%);">+* Enhance compatibility for VGA adaptors</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+intelmetool</span><br><span style="color: hsl(120, 100%, 40%);">+-----------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Add support for Sunrise Point LP</span><br><span style="color: hsl(120, 100%, 40%);">+* Add Intel Boot Guard detection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Toolchain</span><br><span style="color: hsl(120, 100%, 40%);">+---------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* buildgcc now verifies downloaded files against hashes</span><br><span style="color: hsl(120, 100%, 40%);">+* Improve GNAT detection</span><br><span style="color: hsl(120, 100%, 40%);">+* Update binutils to 2.29.1</span><br><span>diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..8a6ab96</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.8.1-relnotes.md</span><br><span>@@ -0,0 +1,179 @@</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot 4.8 & 4.8.1 release notes</span><br><span style="color: hsl(120, 100%, 40%);">+==================================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The 4.8.1 release contains 2 commits: 5f0b80b880 and 6794ce02d4. This</span><br><span style="color: hsl(120, 100%, 40%);">+minor release fixes an issue with adding payloads. The 4.8 release</span><br><span style="color: hsl(120, 100%, 40%);">+covers commit 6dd2f69878 to commit ebdeb4d07d</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Since the last release, the coreboot project had 1198 commits by 124</span><br><span style="color: hsl(120, 100%, 40%);">+authors.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There are PGP signed 4.8 and 4.8.1 tags in the git repository. A branch</span><br><span style="color: hsl(120, 100%, 40%);">+for 4.8 releases (4.8_branch) has been created.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+A big thank you to everyone involved in making this release happen. We</span><br><span style="color: hsl(120, 100%, 40%);">+couldn't have done this without the 35 new commit authors, the</span><br><span style="color: hsl(120, 100%, 40%);">+experienced developers, the many reviewers, documentation writers and</span><br><span style="color: hsl(120, 100%, 40%);">+the fantastic community supporting users on both the mailing list and</span><br><span style="color: hsl(120, 100%, 40%);">+the IRC channel.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+In general, this has been a calm release cycle. Several old devices were</span><br><span style="color: hsl(120, 100%, 40%);">+removed from the master branch early in the release, as they hinder</span><br><span style="color: hsl(120, 100%, 40%);">+development and nobody stepped up doing the porting effort or was</span><br><span style="color: hsl(120, 100%, 40%);">+willing to test coreboot on them. If there is the desire to get a board</span><br><span style="color: hsl(120, 100%, 40%);">+back, it isn't lost as it’s still in the git history.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel i945 platform</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* On Intel 945 devices, native graphics initialization is now skipped</span><br><span style="color: hsl(120, 100%, 40%);">+saving around 100 ms during resume from S3. The OS drivers need to be</span><br><span style="color: hsl(120, 100%, 40%);">+able to handle that. Linux’ i915 driver is able to handle it, but not</span><br><span style="color: hsl(120, 100%, 40%);">+the frame buffer driver.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AMD Stoney Ridge</span><br><span style="color: hsl(120, 100%, 40%);">+----------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Significant cleanup from older AGESA based platforms</span><br><span style="color: hsl(120, 100%, 40%);">+* Fixes to get S3 working</span><br><span style="color: hsl(120, 100%, 40%);">+* Updates to GPIO code to match other modern coreboot chips</span><br><span style="color: hsl(120, 100%, 40%);">+* AGESA interface cleanup - Use native coreboot functions when</span><br><span style="color: hsl(120, 100%, 40%);">+possible</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Lenovo mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+-----------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Started integration of VBT (Video Bios Table) binary files to</span><br><span style="color: hsl(120, 100%, 40%);">+support native graphics initialisation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Internal changes</span><br><span style="color: hsl(120, 100%, 40%);">+----------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Rename of payload type 'payload' to 'simple_elf'</span><br><span style="color: hsl(120, 100%, 40%);">+* Progress in removing typedef device_t</span><br><span style="color: hsl(120, 100%, 40%);">+* Migrated all Intel platforms to a common VBT codebase</span><br><span style="color: hsl(120, 100%, 40%);">+* Ongoing cleanup of whitespace, spelling and formatting</span><br><span style="color: hsl(120, 100%, 40%);">+* Support for PCI in ramstage on non-x86</span><br><span style="color: hsl(120, 100%, 40%);">+* Ongoing Intel platform code deduplication</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Console changes</span><br><span style="color: hsl(120, 100%, 40%);">+---------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Reduce default loglevel to DEBUG</span><br><span style="color: hsl(120, 100%, 40%);">+* Introduce a way for mainboard to override the loglevel</span><br><span style="color: hsl(120, 100%, 40%);">+* Restrict console messages to after console initialization</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Fixed Bugs</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+* qemu-i440fx: Fix ACPI checksum corruption</span><br><span style="color: hsl(120, 100%, 40%);">+* intelmetool: Fix crash, support ME11+ platforms, fix bootguard</span><br><span style="color: hsl(120, 100%, 40%);">+detection</span><br><span style="color: hsl(120, 100%, 40%);">+* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 (https://github.com/nccgroup/TPMGenie)</span><br><span style="color: hsl(120, 100%, 40%);">+* asrock/b75pro3-m: Fixed HDMI</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel/ibexpeak: Fix missing ACPI PIRQ entries</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel/nehalem: Fix freeze during chipset lockdown</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Payloads</span><br><span style="color: hsl(120, 100%, 40%);">+--------</span><br><span style="color: hsl(120, 100%, 40%);">+* Bumped SeaBIOS to 1.11.1</span><br><span style="color: hsl(120, 100%, 40%);">+* Improved TianoCore integration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Security</span><br><span style="color: hsl(120, 100%, 40%);">+--------</span><br><span style="color: hsl(120, 100%, 40%);">+* Start of refactoring the TPM software stack</span><br><span style="color: hsl(120, 100%, 40%);">+* Introduced coreboot security section in kconfig</span><br><span style="color: hsl(120, 100%, 40%);">+* VBoot & TPM code moved into src/security</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intelmetool</span><br><span style="color: hsl(120, 100%, 40%);">+-----------</span><br><span style="color: hsl(120, 100%, 40%);">+* Add Intel Boot Guard status support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Documentation</span><br><span style="color: hsl(120, 100%, 40%);">+-------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Switch from Hugo to Sphinx for the Documentation</span><br><span style="color: hsl(120, 100%, 40%);">+* Working on markdown documentation for https://doc.coreboot.org</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 17 mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+-------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus MAXIMUS_IV_GENE_Z Intel Sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Google ATLAS Intel Kabylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google BIP Intel Geminilake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google CHEZA Qualcomm SDM845</span><br><span style="color: hsl(120, 100%, 40%);">+* Google NOCTURNE Intel Kabylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google OCTOPUS Intel Geminilake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google PHASER Intel Geminilake</span><br><span style="color: hsl(120, 100%, 40%);">+* Google YORP Intel Geminilake</span><br><span style="color: hsl(120, 100%, 40%);">+* HP 8770W Intel Ivybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* HP FOLIO_9470M Intel Ivybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel KBLRVP8 Intel Skylake</span><br><span style="color: hsl(120, 100%, 40%);">+* Lenovo W520 Intel Sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+* OCP MONOLAKE Intel Broadwell DE</span><br><span style="color: hsl(120, 100%, 40%);">+* OCP WEDGE100S Intel Broadwell DE</span><br><span style="color: hsl(120, 100%, 40%);">+* Purism Librem 15 v2 Intel Broadwell</span><br><span style="color: hsl(120, 100%, 40%);">+* Scaleway TAGADA Intel Denverton</span><br><span style="color: hsl(120, 100%, 40%);">+* SiFive HIFIVE_UNLEASHED SiFive FU540</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Removed 39 mainboards</span><br><span style="color: hsl(120, 100%, 40%);">+---------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Abit BE6_II_V2_0</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD DINAR</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD RUMBA</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus DSBF</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus MEW_AM</span><br><span style="color: hsl(120, 100%, 40%);">+* Asus MEW_VM</span><br><span style="color: hsl(120, 100%, 40%);">+* A-trend ATC_6220</span><br><span style="color: hsl(120, 100%, 40%);">+* A-trend ATC_6240</span><br><span style="color: hsl(120, 100%, 40%);">+* AZZA PT_6IBD</span><br><span style="color: hsl(120, 100%, 40%);">+* Biostar M6TBA</span><br><span style="color: hsl(120, 100%, 40%);">+* Compaq DESKPRO_EN_SFF_P600</span><br><span style="color: hsl(120, 100%, 40%);">+* DMP EX</span><br><span style="color: hsl(120, 100%, 40%);">+* ECS P6IWP_FE</span><br><span style="color: hsl(120, 100%, 40%);">+* Gigabyte GA_6BXC</span><br><span style="color: hsl(120, 100%, 40%);">+* Gigabyte GA_6BXE</span><br><span style="color: hsl(120, 100%, 40%);">+* HP E_VECTRA_P2706T</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel D810E2CB</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel EAGLEHEIGHTS</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel MTARVON</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel TRUXTON</span><br><span style="color: hsl(120, 100%, 40%);">+* Iwave RAINBOW_G6</span><br><span style="color: hsl(120, 100%, 40%);">+* Lanner EM8510</span><br><span style="color: hsl(120, 100%, 40%);">+* Lippert FRONTRUNNER</span><br><span style="color: hsl(120, 100%, 40%);">+* Mitac 6513WU</span><br><span style="color: hsl(120, 100%, 40%);">+* MSI MS_6119</span><br><span style="color: hsl(120, 100%, 40%);">+* MSI MS_6147</span><br><span style="color: hsl(120, 100%, 40%);">+* MSI MS_6156</span><br><span style="color: hsl(120, 100%, 40%);">+* MSI MS_6178</span><br><span style="color: hsl(120, 100%, 40%);">+* NEC POWERMATE_2000</span><br><span style="color: hsl(120, 100%, 40%);">+* Nokia IP530</span><br><span style="color: hsl(120, 100%, 40%);">+* RCA RM4100</span><br><span style="color: hsl(120, 100%, 40%);">+* Soyo SY_6BA_PLUS_III</span><br><span style="color: hsl(120, 100%, 40%);">+* Supermicro H8QGI</span><br><span style="color: hsl(120, 100%, 40%);">+* Supermicro H8SCM</span><br><span style="color: hsl(120, 100%, 40%);">+* Supermicro X7DB8</span><br><span style="color: hsl(120, 100%, 40%);">+* Thomson IP1000</span><br><span style="color: hsl(120, 100%, 40%);">+* Tyan S1846</span><br><span style="color: hsl(120, 100%, 40%);">+* Tyan S8226</span><br><span style="color: hsl(120, 100%, 40%);">+* Wyse S50</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Added 2 socs</span><br><span style="color: hsl(120, 100%, 40%);">+------------</span><br><span style="color: hsl(120, 100%, 40%);">+* Qualcomm sdm845</span><br><span style="color: hsl(120, 100%, 40%);">+* SiFive fu540</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Removed 2 socs</span><br><span style="color: hsl(120, 100%, 40%);">+--------------</span><br><span style="color: hsl(120, 100%, 40%);">+* DMP vortex86ex</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel sch</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Removed 5 processors</span><br><span style="color: hsl(120, 100%, 40%);">+--------------------</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD agesa-family15</span><br><span style="color: hsl(120, 100%, 40%);">+* AMD geode-gx2</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel ep80579</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel model-f0x</span><br><span style="color: hsl(120, 100%, 40%);">+* Intel model-f1x</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Statistics</span><br><span style="color: hsl(120, 100%, 40%);">+----------</span><br><span style="color: hsl(120, 100%, 40%);">+* Total commits: 1198</span><br><span style="color: hsl(120, 100%, 40%);">+* Average Commits per day: 9.85</span><br><span style="color: hsl(120, 100%, 40%);">+* Total authors: 124</span><br><span style="color: hsl(120, 100%, 40%);">+* New authors: 35</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines added: 386113</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines removed: 291201</span><br><span style="color: hsl(120, 100%, 40%);">+* Total lines difference: 94912</span><br><span>diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md</span><br><span>new file mode 100644</span><br><span>index 0000000..788d695</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/coreboot-4.9-relnotes.md</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot 4.9 release notes</span><br><span style="color: hsl(120, 100%, 40%);">+==========================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The 4.9 release is planned for November 2018</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Update this document with changes that should be in the release</span><br><span style="color: hsl(120, 100%, 40%);">+notes.</span><br><span style="color: hsl(120, 100%, 40%);">+* Please use Markdown.</span><br><span style="color: hsl(120, 100%, 40%);">+* See the [4.7](coreboot-4.7-relnotes.md) and [4.8](coreboot-4.8.1-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+ release notes for the general format.</span><br><span style="color: hsl(120, 100%, 40%);">+* The chip and board additions and removals will be updated right</span><br><span style="color: hsl(120, 100%, 40%);">+before the release, so those do not need to be added.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+General changes</span><br><span style="color: hsl(120, 100%, 40%);">+---------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Toolchain</span><br><span style="color: hsl(120, 100%, 40%);">+---------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Update IASL to version 10280531</span><br><span>diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md</span><br><span>new file mode 100644</span><br><span>index 0000000..fd95fd7</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/releases/index.md</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Release notes for previous releases</span><br><span style="color: hsl(120, 100%, 40%);">+===================================</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.1 - July 2015](coreboot-4.1-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.2 - October 2015](coreboot-4.2-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.3 - January 2016](coreboot-4.3-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.4 - May 2016](coreboot-4.4-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.5 - October 2016](coreboot-4.5-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.6 - April 2017](coreboot-4.6-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.7 - January 2018](coreboot-4.7-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Upcoming release</span><br><span style="color: hsl(120, 100%, 40%);">+----------------</span><br><span style="color: hsl(120, 100%, 40%);">+### * [4.9 - November 2018](coreboot-4.9-relnotes.md)</span><br><span style="color: hsl(120, 100%, 40%);">+Please add to the release notes as changes are added:</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26799">change 26799</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26799"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: I7440a3130f2f7d80c4434d2b5a918e62bbd08fbb </div>
<div style="display:none"> Gerrit-Change-Number: 26799 </div>
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<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>