<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26790">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car/non-evict: Improve a few things<br><br>This improve the following:<br>- Improve readability for clearing fixed MTRR's<br>- Compute PHYSMASK high during runtime<br>- Cache the whole ROM_SIZE instead of XIP_ROM_SIZE<br><br>Change-Id: Ifaed96b41fab973fa541de1c4f005d6f0af5254f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/non-evict/cache_as_ram.S<br>1 file changed, 60 insertions(+), 29 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/26790/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span>index a884479..27121d0 100644</span><br><span>--- a/src/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span>+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span>@@ -3,6 +3,7 @@</span><br><span> *</span><br><span> * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span> * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com></span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -53,18 +54,16 @@</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x22)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Zero out all fixed range MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $mtrr_table, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $((mtrr_table_end - mtrr_table) >> 1), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">-clear_mtrrs:</span><br><span style="color: hsl(0, 100%, 40%);">- movw (%esi), %bx</span><br><span style="color: hsl(0, 100%, 40%);">- movzx %bx, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear/disable fixed MTRRs */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $fixed_mtrr_list_size, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+clear_fixed_mtrr:</span><br><span style="color: hsl(120, 100%, 40%);">+ add $-2, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ movzwl fixed_mtrr_list(%ebx), %ecx</span><br><span> wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- add $2, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- dec %edi</span><br><span style="color: hsl(0, 100%, 40%);">- jnz clear_mtrrs</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_fixed_mtrr</span><br><span> </span><br><span> /* Zero out all variable range MTRRs. */</span><br><span> movl $MTRR_CAP_MSR, %ecx</span><br><span>@@ -81,6 +80,39 @@</span><br><span> dec %edi</span><br><span> jnz clear_var_mtrrs</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Determine CPU_ADDR_BITS and load PHYSMASK high</span><br><span style="color: hsl(120, 100%, 40%);">+ * word to %edx.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x80000000, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid</span><br><span style="color: hsl(120, 100%, 40%);">+ cmpl $0x80000008, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jc addrsize_no_MSR</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x80000008, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid</span><br><span style="color: hsl(120, 100%, 40%);">+ movb %al, %cl</span><br><span style="color: hsl(120, 100%, 40%);">+ sub $32, %cl</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $1, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ shl %cl, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ subl $1, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp addrsize_set_high</span><br><span style="color: hsl(120, 100%, 40%);">+addrsize_no_MSR:</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */</span><br><span style="color: hsl(120, 100%, 40%);">+ jz addrsize_set_high</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x0f, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Preload high word of address mask (in %edx) for Variable</span><br><span style="color: hsl(120, 100%, 40%);">+ * MTRRs 0 and 1 and enable local APIC at default base.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+addrsize_set_high:</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_MASK(0), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> post_code(0x23)</span><br><span> /* Set Cache-as-RAM base address. */</span><br><span> movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span>@@ -91,8 +123,8 @@</span><br><span> post_code(0x24)</span><br><span> /* Set Cache-as-RAM mask. */</span><br><span> movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span> movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x25)</span><br><span>@@ -120,7 +152,6 @@</span><br><span> movl $CACHE_AS_RAM_BASE, %esi</span><br><span> movl %esi, %edi</span><br><span> movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- // movl $0x23322332, %eax</span><br><span> xorl %eax, %eax</span><br><span> rep stosl</span><br><span> </span><br><span>@@ -139,18 +170,12 @@</span><br><span> /* Enable cache for our code in Flash because we do XIP here */</span><br><span> movl $MTRR_PHYS_BASE(1), %ecx</span><br><span> xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(0, 100%, 40%);">- * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $copy_and_run, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_TYPE_WRPROT, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax</span><br><span> wrmsr</span><br><span> </span><br><span> movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x28)</span><br><span>@@ -181,12 +206,18 @@</span><br><span> hlt</span><br><span> jmp .Lhlt</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fixed MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x250, 0x258, 0x259</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x268, 0x269, 0x26A</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26B, 0x26C, 0x26D</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26E, 0x26F</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table_end:</span><br><span style="color: hsl(120, 100%, 40%);">+fixed_mtrr_list:</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_64K_00000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_16K_80000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_16K_A0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_C0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_C8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_D0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_D8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_E0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_E8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_F0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_F8000</span><br><span style="color: hsl(120, 100%, 40%);">+fixed_mtrr_list_size = . - fixed_mtrr_list</span><br><span> </span><br><span> _cache_as_ram_setup_end:</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26790">change 26790</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26790"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifaed96b41fab973fa541de1c4f005d6f0af5254f </div>
<div style="display:none"> Gerrit-Change-Number: 26790 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>