<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26789">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support<br><br>Prepare a common cache as ram for CPU's featuring a Non eviction mode<br>MSR.<br><br>Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/cpu/intel/car/non-evict/cache_as_ram.S<br>A src/cpu/intel/car/non-evict/exit_car.S<br>M src/cpu/intel/haswell/Makefile.inc<br>M src/cpu/intel/model_2065x/Makefile.inc<br>M src/cpu/intel/model_206ax/Makefile.inc<br>5 files changed, 264 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26789/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span>new file mode 100644</span><br><span>index 0000000..a884479</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span>@@ -0,0 +1,192 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NoEvictMod_MSR 0x2e0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.code32</span><br><span style="color: hsl(120, 100%, 40%);">+_cache_as_ram_setup:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Save the BIST result. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %ebp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cache_as_ram:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x20)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Send INIT IPI to all excluding ourself. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x000C4500, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0xFEE00300, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, (%esi)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* All CPUs need to be in Wait for SIPI state */</span><br><span style="color: hsl(120, 100%, 40%);">+wait_for_sipi:</span><br><span style="color: hsl(120, 100%, 40%);">+ movl (%esi), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ bt $12, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jc wait_for_sipi</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x21)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clean-up MTRR_DEF_TYPE_MSR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x22)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Zero out all fixed range MTRRs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $mtrr_table, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+clear_mtrrs:</span><br><span style="color: hsl(120, 100%, 40%);">+ movw (%esi), %bx</span><br><span style="color: hsl(120, 100%, 40%);">+ movzx %bx, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ add $2, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ dec %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_mtrrs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Zero out all variable range MTRRs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_CAP_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $0xff, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ shl $1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x200, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+clear_var_mtrrs:</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ add $1, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ dec %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_var_mtrrs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x23)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x24)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x25)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable MTRR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ invd</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable the 'no eviction' mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $~2, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear the cache memory region. This will also fill up the cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CACHE_AS_RAM_BASE, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %esi, %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ // movl $0x23322332, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ rep stosl</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable the 'no eviction run' state */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $3, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x26)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Cache-as-RAM mode by disabling cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable cache for our code in Flash because we do XIP here */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_BASE(1), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(120, 100%, 40%);">+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $copy_and_run, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $MTRR_TYPE_WRPROT, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x28)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup the stack. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Restore the BIST result. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %ebp, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %esp, %ebp</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+before_romstage:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x29)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call romstage.c main function. */</span><br><span style="color: hsl(120, 100%, 40%);">+ call romstage_main</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should never see this postcode */</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.Lhlt:</span><br><span style="color: hsl(120, 100%, 40%);">+ hlt</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+mtrr_table:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fixed MTRRs */</span><br><span style="color: hsl(120, 100%, 40%);">+ .word 0x250, 0x258, 0x259</span><br><span style="color: hsl(120, 100%, 40%);">+ .word 0x268, 0x269, 0x26A</span><br><span style="color: hsl(120, 100%, 40%);">+ .word 0x26B, 0x26C, 0x26D</span><br><span style="color: hsl(120, 100%, 40%);">+ .word 0x26E, 0x26F</span><br><span style="color: hsl(120, 100%, 40%);">+mtrr_table_end:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+_cache_as_ram_setup_end:</span><br><span>diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S</span><br><span>new file mode 100644</span><br><span>index 0000000..5eb2515</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/non-evict/exit_car.S</span><br><span>@@ -0,0 +1,55 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NoEvictMod_MSR 0x2e0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.code32</span><br><span style="color: hsl(120, 100%, 40%);">+.global chipset_teardown_car</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chipset_teardown_car:</span><br><span style="color: hsl(120, 100%, 40%);">+ pop %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x30)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable MTRR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable the no eviction run state */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $~2, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $~1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x32)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Return to caller. */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%esp</span><br><span>diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc</span><br><span>index bb0f376..dc7170b 100644</span><br><span>--- a/src/cpu/intel/haswell/Makefile.inc</span><br><span>+++ b/src/cpu/intel/haswell/Makefile.inc</span><br><span>@@ -14,7 +14,12 @@</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c</span><br><span> smm-y += monotonic_timer.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span> cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/non-evict/exit_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span> </span><br><span> subdirs-y += ../../x86/tsc</span><br><span> subdirs-y += ../../x86/mtrr</span><br><span>diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc</span><br><span>index 137d1c9..44d7460 100644</span><br><span>--- a/src/cpu/intel/model_2065x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_2065x/Makefile.inc</span><br><span>@@ -20,5 +20,11 @@</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span> cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/non-evict/exit_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>index 1e04554..0e2733e 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>@@ -17,5 +17,11 @@</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span> cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/non-evict/exit_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += ../car/romstage.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26789">change 26789</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26789"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7 </div>
<div style="display:none"> Gerrit-Change-Number: 26789 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>