<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26728">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/pch/gspi: Move gspi functionality to common PCH<br><br>GSPI functionality is common for platforms using common base PCH code.<br>Thus moving this functionality from individual soc to common PCH base.<br><br>BUG=none<br>BRANCH=none<br>TEST=check if patch builds and KBL, CNL boots with this patch.<br><br>Change-Id: I2cf65d56451afac5258c7127854b5fc7f4d84bd1<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/common/pch/Kconfig<br>A src/soc/intel/common/pch/gspi/Kconfig<br>A src/soc/intel/common/pch/gspi/Makefile.inc<br>R src/soc/intel/common/pch/gspi/gspi.c<br>M src/soc/intel/skylake/Makefile.inc<br>D src/soc/intel/skylake/gspi.c<br>7 files changed, 13 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/26728/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index f8f9198..4cce5c3 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -14,7 +14,6 @@</span><br><span> bootblock-y += pmutil.c</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span> bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gspi.c</span><br><span> bootblock-y += i2c.c</span><br><span> bootblock-y += memmap.c</span><br><span> bootblock-y += spi.c</span><br><span>@@ -24,7 +23,6 @@</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gspi.c</span><br><span> romstage-y += i2c.c</span><br><span> romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span>@@ -39,7 +37,6 @@</span><br><span> ramstage-y += finalize.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += graphics.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gspi.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += i2c.c</span><br><span> ramstage-y += lockdown.c</span><br><span>@@ -67,7 +64,6 @@</span><br><span> postcar-y += pmutil.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-verstage-y += gspi.c</span><br><span> verstage-y += i2c.c</span><br><span> verstage-y += pmutil.c</span><br><span> verstage-y += spi.c</span><br><span>diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig</span><br><span>index ead0536..9014647 100644</span><br><span>--- a/src/soc/intel/common/pch/Kconfig</span><br><span>+++ b/src/soc/intel/common/pch/Kconfig</span><br><span>@@ -44,5 +44,5 @@</span><br><span>    select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span>   select SOC_INTEL_COMMON_BLOCK_XHCI</span><br><span>   select SOC_INTEL_COMMON_PCH_LOCKDOWN</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+  select SOC_INTEL_COMMON_PCH_GSPI</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/common/pch/gspi/Kconfig b/src/soc/intel/common/pch/gspi/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..c07611b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/pch/gspi/Kconfig</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_PCH_GSPI</span><br><span style="color: hsl(120, 100%, 40%);">+      bool</span><br><span style="color: hsl(120, 100%, 40%);">+  default n</span><br><span style="color: hsl(120, 100%, 40%);">+     help</span><br><span style="color: hsl(120, 100%, 40%);">+    This option allows to have gspi configuration for supported PCH.</span><br><span>diff --git a/src/soc/intel/common/pch/gspi/Makefile.inc b/src/soc/intel/common/pch/gspi/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..19ff891</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/pch/gspi/Makefile.inc</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c</span><br><span>diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/common/pch/gspi/gspi.c</span><br><span>similarity index 92%</span><br><span>rename from src/soc/intel/cannonlake/gspi.c</span><br><span>rename to src/soc/intel/common/pch/gspi/gspi.c</span><br><span>index c5998b5..99fd2b4 100644</span><br><span>--- a/src/soc/intel/cannonlake/gspi.c</span><br><span>+++ b/src/soc/intel/common/pch/gspi/gspi.c</span><br><span>@@ -13,7 +13,6 @@</span><br><span>  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #include <intelblocks/gspi.h></span><br><span> #include <soc/pci_devs.h></span><br><span> </span><br><span>@@ -24,8 +23,10 @@</span><br><span>                 return PCH_DEVFN_GSPI0;</span><br><span>      case 1:</span><br><span>              return PCH_DEVFN_GSPI1;</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)</span><br><span>        case 2:</span><br><span>              return PCH_DEVFN_GSPI2;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>      }</span><br><span>    return -1;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc</span><br><span>index 89e48f1..8f673c3 100644</span><br><span>--- a/src/soc/intel/skylake/Makefile.inc</span><br><span>+++ b/src/soc/intel/skylake/Makefile.inc</span><br><span>@@ -15,21 +15,18 @@</span><br><span> bootblock-y += bootblock/pch.c</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span> bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gspi.c</span><br><span> bootblock-y += p2sb.c</span><br><span> bootblock-y += pmutil.c</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += lpc.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-verstage-y += gspi.c</span><br><span> verstage-y += pmutil.c</span><br><span> verstage-y += i2c.c</span><br><span> verstage-y += spi.c</span><br><span> verstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gspi.c</span><br><span> romstage-y += i2c.c</span><br><span> romstage-y += memmap.c</span><br><span> romstage-y += me.c</span><br><span>@@ -47,7 +44,6 @@</span><br><span> ramstage-y += elog.c</span><br><span> ramstage-y += finalize.c</span><br><span> ramstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gspi.c</span><br><span> ramstage-y += i2c.c</span><br><span> ramstage-y += graphics.c</span><br><span> ramstage-y += irq.c</span><br><span>@@ -76,7 +72,6 @@</span><br><span> smm-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> postcar-y += memmap.c</span><br><span style="color: hsl(0, 100%, 40%);">-postcar-y += gspi.c</span><br><span> postcar-y += spi.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c</span><br><span>deleted file mode 100644</span><br><span>index 3fb7c50..0000000</span><br><span>--- a/src/soc/intel/skylake/gspi.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,28 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/gspi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- switch (gspi_bus) {</span><br><span style="color: hsl(0, 100%, 40%);">-     case 0:</span><br><span style="color: hsl(0, 100%, 40%);">-         return PCH_DEVFN_GSPI0;</span><br><span style="color: hsl(0, 100%, 40%);">- case 1:</span><br><span style="color: hsl(0, 100%, 40%);">-         return PCH_DEVFN_GSPI1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-       return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26728">change 26728</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26728"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2cf65d56451afac5258c7127854b5fc7f4d84bd1 </div>
<div style="display:none"> Gerrit-Change-Number: 26728 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>