<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26707">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car/cache_as_ram_ht.inc: cache the whole ROM_SIZE<br><br>Change-Id: Ieeaee7b47fc9c31e9abae8c49e16f62bee7c76d5<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/cache_as_ram_ht.inc<br>1 file changed, 2 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26707/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>index 58dbf29..7fc92fc 100644</span><br><span>--- a/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>+++ b/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>@@ -334,18 +334,13 @@</span><br><span> /* Enable cache for our code in Flash because we do XIP here */</span><br><span> movl $MTRR_PHYS_BASE(1), %ecx</span><br><span> xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(0, 100%, 40%);">- * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $copy_and_run, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(-CACHE_ROM_SIZE), %eax</span><br><span> orl $MTRR_TYPE_WRPROT, %eax</span><br><span> wrmsr</span><br><span> </span><br><span> movl $MTRR_PHYS_MASK(1), %ecx</span><br><span> rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x2e)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26707">change 26707</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26707"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ieeaee7b47fc9c31e9abae8c49e16f62bee7c76d5 </div>
<div style="display:none"> Gerrit-Change-Number: 26707 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>