<p>Vincent Palatin has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26684">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/nocturne: configure the FPMCU interface<br><br>The FPMCU is using the standard cros-ec-spi interface on GSPI1.<br>Configure the GPIOs controlling the MCU too.<br><br>We need to be able to wake from S3 on the MCU interrupt, re-configure<br>GPE0 DW0 to point to GPP_C bank.<br><br>BRANCH=poppy<br>BUG=b:79666174<br>TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',<br>verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'<br>then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs<br>with the flash_fp_mcu script.<br><br>Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5<br>Signed-off-by: Vincent Palatin <vpalatin@chromium.org><br>---<br>M src/mainboard/google/poppy/variants/nocturne/devicetree.cb<br>M src/mainboard/google/poppy/variants/nocturne/gpio.c<br>2 files changed, 25 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26684/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>index 621bbe4..91e8b46 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>@@ -11,7 +11,7 @@</span><br><span> # Note that GPE events called out in ASL code rely on this</span><br><span> # route. i.e. If this route changes then the affected GPE</span><br><span> # offset bits also need to be changed.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_C"</span><br><span> register "gpe0_dw1" = "GPP_D"</span><br><span> register "gpe0_dw2" = "GPP_E"</span><br><span> </span><br><span>@@ -326,7 +326,23 @@</span><br><span> device spi 0 on end</span><br><span> end</span><br><span> end # GSPI #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.3 on end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "uid" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cros-ec-spi""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_09" # GPP_C9</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_delay_ms" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_off_delay_ms" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_delay_ms" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_off_delay_ms" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_resource" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #1</span><br><span> device pci 1e.4 on end # eMMC</span><br><span> device pci 1e.5 off end # SDIO</span><br><span> device pci 1e.6 off end # SDCard</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>index bd38a20..8a15756 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>@@ -39,8 +39,8 @@</span><br><span> PAD_CFG_NC(GPP_A10),</span><br><span> /* A11 : PCH_FP_PWR_EN */</span><br><span> PAD_CFG_GPO(GPP_A11, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A12 : FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_A12, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A12 : ISH_GP6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A12),</span><br><span> /* A13 : SUSWARN# ==> SUSWARN_L */</span><br><span> PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span> /* A14 : ESPI_RESET# */</span><br><span>@@ -108,7 +108,7 @@</span><br><span> /* B21 : GSPI1_MISO ==> PCH_FPMCU_SPI_MISO_R */</span><br><span> PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),</span><br><span> /* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),</span><br><span> /* B23 : SM1ALERT# ==> PCHHOT# */</span><br><span> PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2),</span><br><span> </span><br><span>@@ -129,13 +129,13 @@</span><br><span> /* C7 : SM1DATA ==> NC */</span><br><span> PAD_CFG_NC(GPP_C7),</span><br><span> /* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C8, 0, DEEP),</span><br><span> /* C9 : UART0_TXD ==> FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C9),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT),</span><br><span> /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C10),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C10, 1, DEEP),</span><br><span> /* C11 : UART0_CTS# ==> FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C11),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_INVERT(GPP_C11, NONE, DEEP),</span><br><span> /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),</span><br><span> /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26684">change 26684</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 </div>
<div style="display:none"> Gerrit-Change-Number: 26684 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vincent Palatin <vpalatin@chromium.org> </div>