<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26717">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Use postcar stage to tear down CAR<br><br>Also remove unused code in model_6e/cache_as_ram.inc<br><br>Change-Id: Ifa3a90b5ba3c873683ba3e5b8faa5025b64929de<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_6ex/cache_as_ram.inc<br>M src/cpu/intel/socket_441/Makefile.inc<br>M src/cpu/intel/socket_LGA775/Makefile.inc<br>M src/cpu/intel/socket_mFCPGA478/Makefile.inc<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/Makefile.inc<br>M src/northbridge/intel/i945/ram_calc.c<br>7 files changed, 12 insertions(+), 117 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/26717/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>index e4ff0fc..b2d7628 100644</span><br><span>--- a/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>@@ -155,115 +155,6 @@</span><br><span> post_code(0x29)</span><br><span> /* Call romstage.c main function. */</span><br><span> call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear all of the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- clr %eax</span><br><span style="color: hsl(0, 100%, 40%);">- clr %edx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 2f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 2b</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3a)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache again. */</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span> </span><br><span> .Lhlt:</span><br><span> post_code(POST_DEAD_CODE)</span><br><span>diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc</span><br><span>index dbf300b..63d373e 100644</span><br><span>--- a/src/cpu/intel/socket_441/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_441/Makefile.inc</span><br><span>@@ -9,4 +9,5 @@</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc</span><br><span>index 78a2f32..e81ecc4 100644</span><br><span>--- a/src/cpu/intel/socket_LGA775/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_LGA775/Makefile.inc</span><br><span>@@ -14,5 +14,5 @@</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc</span><br><span style="color: hsl(0, 100%, 40%);">-postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc</span><br><span>index 6056d3c..14f96a9 100644</span><br><span>--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc</span><br><span>@@ -12,4 +12,5 @@</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig</span><br><span>index 482f98a..e04d0c3 100644</span><br><span>--- a/src/northbridge/intel/i945/Kconfig</span><br><span>+++ b/src/northbridge/intel/i945/Kconfig</span><br><span>@@ -28,6 +28,8 @@</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select INTEL_EDID</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SUBTYPE_I945GC</span><br><span> def_bool n</span><br><span>diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc</span><br><span>index 0e4fcfc..ffeabdc 100644</span><br><span>--- a/src/northbridge/intel/i945/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/i945/Makefile.inc</span><br><span>@@ -29,4 +29,6 @@</span><br><span> </span><br><span> smm-y += udelay.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 990df97..6b04f50 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -78,8 +78,6 @@</span><br><span> return ggc2uma[gms] << 10;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span> void *setup_stack_and_mtrrs(void)</span><br><span>@@ -87,7 +85,7 @@</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, 1*KiB))</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -106,8 +104,8 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26717">change 26717</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifa3a90b5ba3c873683ba3e5b8faa5025b64929de </div>
<div style="display:none"> Gerrit-Change-Number: 26717 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>