<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26716">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Use postcar stage to tear down CAR<br><br>Change-Id: I4c5c5648fd6e54e61f2bd532624331cdd0d52ece<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/cache_as_ram_ht.inc<br>M src/cpu/intel/socket_LGA775/Makefile.inc<br>M src/northbridge/intel/x4x/Kconfig<br>M src/northbridge/intel/x4x/Makefile.inc<br>M src/northbridge/intel/x4x/ram_calc.c<br>5 files changed, 14 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/26716/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>index 0eb58d1..5f2a91a 100644</span><br><span>--- a/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>+++ b/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>@@ -348,6 +348,10 @@</span><br><span> post_code(0x2f)</span><br><span> /* Call romstage.c main function. */</span><br><span> call romstage_main</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_POSTCAR_STAGE)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should never be reached */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> /* Save return value from romstage_main. It contains the stack to use</span><br><span> * after cache-as-ram is torn down. It also contains the information</span><br><span> * for setting up MTRRs. */</span><br><span>diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc</span><br><span>index ffcd1cb..78a2f32 100644</span><br><span>--- a/src/cpu/intel/socket_LGA775/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_LGA775/Makefile.inc</span><br><span>@@ -14,5 +14,5 @@</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += ../car/romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig</span><br><span>index d9dbdc9..610f785 100644</span><br><span>--- a/src/northbridge/intel/x4x/Kconfig</span><br><span>+++ b/src/northbridge/intel/x4x/Kconfig</span><br><span>@@ -29,6 +29,8 @@</span><br><span> select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select CACHE_MRC_SETTINGS</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span>diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc</span><br><span>index 1f7e483..3118b09 100644</span><br><span>--- a/src/northbridge/intel/x4x/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/x4x/Makefile.inc</span><br><span>@@ -29,4 +29,6 @@</span><br><span> ramstage-y += gma.c</span><br><span> ramstage-y += northbridge.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>index 1009372..b5efabe 100644</span><br><span>--- a/src/northbridge/intel/x4x/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>@@ -103,8 +103,6 @@</span><br><span> return (void *) top_of_ram;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span> void *setup_stack_and_mtrrs(void)</span><br><span>@@ -112,7 +110,7 @@</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, 1*KiB))</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -131,8 +129,8 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26716">change 26716</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4c5c5648fd6e54e61f2bd532624331cdd0d52ece </div>
<div style="display:none"> Gerrit-Change-Number: 26716 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>