<p><a href="https://review.coreboot.org/26603">View Change</a></p><p>14 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/agesa/family14/chip.h">File src/northbridge/amd/agesa/family14/chip.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/agesa/family14/chip.h@30">Patch Set #7, Line 30:</a> <code style="font-family:monospace,monospace"> * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdht/h3gtopo.h">File src/northbridge/amd/amdht/h3gtopo.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdht/h3gtopo.h@259">Patch Set #7, Line 259:</a> <code style="font-family:monospace,monospace"> 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbridge.c">File src/northbridge/amd/amdk8/northbridge.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbridge.c@993">Patch Set #7, Line 993:</a> <code style="font-family:monospace,monospace"> if (!is_cpu_pre_e0())</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">suspect code indent for conditional statements (40, 49)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbridge.c@995">Patch Set #7, Line 995:</a> <code style="font-family:monospace,monospace"> sizek += hoist_memory(mmio_basek, i);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbridge.c@1220">Patch Set #7, Line 1220:</a> <code style="font-family:monospace,monospace"> e0_later_single_core = is_e0_later_in_bsp(i); // single core</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbridge.c@1222">Patch Set #7, Line 1222:</a> <code style="font-family:monospace,monospace"> e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/raminit.c">File src/northbridge/amd/amdk8/raminit.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/raminit.c@1310">Patch Set #7, Line 1310:</a> <code style="font-family:monospace,monospace"> uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mct_d.c">File src/northbridge/amd/amdmct/mct/mct_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mct_d.c@3756">Patch Set #7, Line 3756:</a> <code style="font-family:monospace,monospace"> * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mctdqs_d.c">File src/northbridge/amd/amdmct/mct/mctdqs_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mctdqs_d.c@464">Patch Set #7, Line 464:</a> <code style="font-family:monospace,monospace"> BanksPresent = 1; /* flag for at least one bank is present */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c">File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c@7912">Patch Set #7, Line 7912:</a> <code style="font-family:monospace,monospace"> * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c">File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@118">Patch Set #7, Line 118:</a> <code style="font-family:monospace,monospace"> OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@123">Patch Set #7, Line 123:</a> <code style="font-family:monospace,monospace"> /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c">File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@699">Patch Set #7, Line 699:</a> <code style="font-family:monospace,monospace"> // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/lx/northbridgeinit.c">File src/northbridge/amd/lx/northbridgeinit.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/lx/northbridgeinit.c@597">Patch Set #7, Line 597:</a> <code style="font-family:monospace,monospace"> * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/26603">change 26603</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935 </div>
<div style="display:none"> Gerrit-Change-Number: 26603 </div>
<div style="display:none"> Gerrit-PatchSet: 7 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Wed, 30 May 2018 07:13:04 +0000 </div>
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