<p><a href="https://review.coreboot.org/26466">View Change</a></p><p>12 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c">File src/mainboard/amd/south_station/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@24">Patch Set #2, Line 24:</a> <code style="font-family:monospace,monospace">                                       VOID *ConfigPtr);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">need consistent spacing around '*' (ctx:WxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@157">Patch Set #2, Line 157:</a> <code style="font-family:monospace,monospace">                     Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@163">Patch Set #2, Line 163:</a> <code style="font-family:monospace,monospace">                      Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@173">Patch Set #2, Line 173:</a> <code style="font-family:monospace,monospace">                      Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@179">Patch Set #2, Line 179:</a> <code style="font-family:monospace,monospace">                  Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@189">Patch Set #2, Line 189:</a> <code style="font-family:monospace,monospace">                  Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/BiosCallOuts.c@195">Patch Set #2, Line 195:</a> <code style="font-family:monospace,monospace">                     Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/OemCustomize.c">File src/mainboard/amd/south_station/OemCustomize.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/OemCustomize.c@60">Patch Set #2, Line 60:</a> <code style="font-family:monospace,monospace">   }</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Statements should start on a tabstop</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/OemCustomize.c@75">Patch Set #2, Line 75:</a> <code style="font-family:monospace,monospace">        }</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Statements should start on a tabstop</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/mptable.c">File src/mainboard/amd/south_station/mptable.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/mptable.c@26">Patch Set #2, Line 26:</a> <code style="font-family:monospace,monospace"> [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,        /* INTA# - INTH# */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/mptable.c@27">Patch Set #2, Line 27:</a> <code style="font-family:monospace,monospace">        [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,        /* Misc-nil,0,1,2, INT from Serial irq */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26466/2/src/mainboard/amd/south_station/mptable.c@81">Patch Set #2, Line 81:</a> <code style="font-family:monospace,monospace">  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/26466">change 26466</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26466"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: Iae457237ef104736478eface4d91dd282fd866ea </div>
<div style="display:none"> Gerrit-Change-Number: 26466 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Tue, 29 May 2018 19:45:50 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
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