<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26604">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/southbridge: Get rid of whitespace befor tab<br><br>Change-Id: I9a2eada93f05b6a4adac3406c33b6e109b733324<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/agesa/hudson/resume.c<br>M src/southbridge/amd/cimx/sb800/acpi/fch.asl<br>M src/southbridge/amd/cimx/sb800/late.c<br>M src/southbridge/amd/cimx/sb900/late.c<br>M src/southbridge/amd/cs5536/cs5536.c<br>M src/southbridge/amd/cs5536/cs5536.h<br>M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h<br>M src/southbridge/amd/pi/hudson/early_setup.c<br>M src/southbridge/amd/pi/hudson/hudson.h<br>M src/southbridge/amd/rs690/early_setup.c<br>M src/southbridge/amd/rs690/gfx.c<br>M src/southbridge/amd/rs690/rs690.c<br>M src/southbridge/amd/rs690/rs690.h<br>M src/southbridge/amd/rs780/early_setup.c<br>M src/southbridge/amd/rs780/gfx.c<br>M src/southbridge/amd/rs780/rs780.c<br>M src/southbridge/amd/rs780/rs780.h<br>M src/southbridge/amd/sb600/early_setup.c<br>M src/southbridge/amd/sb700/sm.c<br>M src/southbridge/amd/sb700/usb.c<br>M src/southbridge/amd/sb800/usb.c<br>M src/southbridge/amd/sr5650/cmn.h<br>M src/southbridge/amd/sr5650/pcie.c<br>M src/southbridge/amd/sr5650/sr5650.c<br>M src/southbridge/broadcom/bcm5785/lpc.c<br>M src/southbridge/intel/bd82x6x/acpi/pch.asl<br>M src/southbridge/intel/bd82x6x/me.h<br>M src/southbridge/intel/bd82x6x/smihandler.c<br>M src/southbridge/intel/common/pciehp.c<br>M src/southbridge/intel/common/smbus.c<br>M src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl<br>M src/southbridge/intel/fsp_bd82x6x/me.h<br>M src/southbridge/intel/fsp_bd82x6x/smi.c<br>M src/southbridge/intel/fsp_bd82x6x/smihandler.c<br>M src/southbridge/intel/fsp_i89xx/acpi/pch.asl<br>M src/southbridge/intel/fsp_i89xx/me.h<br>M src/southbridge/intel/fsp_i89xx/smihandler.c<br>M src/southbridge/intel/fsp_rangeley/acpi/soc.asl<br>M src/southbridge/intel/i82801dx/smihandler.c<br>M src/southbridge/intel/i82801gx/acpi/ich7.asl<br>M src/southbridge/intel/i82801ix/acpi/ich9.asl<br>M src/southbridge/intel/i82801ix/smihandler.c<br>M src/southbridge/intel/i82801jx/acpi/ich10.asl<br>M src/southbridge/intel/i82801jx/smihandler.c<br>M src/southbridge/intel/i82870/82870.h<br>M src/southbridge/intel/ibexpeak/me.h<br>M src/southbridge/intel/ibexpeak/smi.c<br>M src/southbridge/intel/ibexpeak/smihandler.c<br>M src/southbridge/intel/lynxpoint/acpi/pch.asl<br>M src/southbridge/intel/lynxpoint/me.h<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/smihandler.c<br>M src/southbridge/via/common/early_smbus_print_error.c<br>M src/southbridge/via/k8t890/bridge.c<br>M src/southbridge/via/k8t890/ctrl.c<br>M src/southbridge/via/k8t890/dram.c<br>M src/southbridge/via/vt8237r/early_smbus.c<br>M src/southbridge/via/vt8237r/lpc.c<br>M src/southbridge/via/vt8237r/nic.c<br>M src/southbridge/via/vt8237r/usb.c<br>M src/southbridge/via/vt8237r/vt8237r.h<br>61 files changed, 131 insertions(+), 131 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/26604/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c</span><br><span>index 2528294..84a5543 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/resume.c</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/resume.c</span><br><span>@@ -104,8 +104,8 @@</span><br><span> FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable;</span><br><span> FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- FchParams->Usb.Xhci1Enable = FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams->Usb.Xhci1Enable = FALSE;</span><br><span> </span><br><span> #if DUMP_FCH_SETTING</span><br><span> int i;</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl</span><br><span>index 816988b..6f0826f 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl</span><br><span>@@ -178,7 +178,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>@@ -298,9 +298,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c</span><br><span>index ebc6ba1..30cddb2 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/late.c</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/late.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include <device/pci_ehci.h></span><br><span> #include "lpc.h" /* lpc_read_resources */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platform Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platform Specific Definitions */</span><br><span> #include "cfg.h" /* sb800 Cimx configuration */</span><br><span> #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */</span><br><span> #include "sb_cimx.h" /* AMD CIMX wrapper entries */</span><br><span>@@ -352,13 +352,13 @@</span><br><span> switch (dev->path.pci.devfn) {</span><br><span> case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */</span><br><span> if (dev->enabled) {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;</span><br><span> if (1 == sb_chip->boot_switch_sata_ide)</span><br><span> sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.</span><br><span> else if (0 == sb_chip->boot_switch_sata_ide)</span><br><span> sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;</span><br><span> }</span><br><span> break;</span><br><span> </span><br><span>@@ -387,11 +387,11 @@</span><br><span> </span><br><span> case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */</span><br><span> if (dev->enabled) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (AZALIA_DISABLE == sb_config->AzaliaController) {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->AzaliaController = AZALIA_AUTO;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (AZALIA_DISABLE == sb_config->AzaliaController) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->AzaliaController = AZALIA_AUTO;</span><br><span> }</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->AzaliaController = AZALIA_DISABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->AzaliaController = AZALIA_DISABLE;</span><br><span> }</span><br><span> break;</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c</span><br><span>index e792fe3..d535cb6 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb900/late.c</span><br><span>+++ b/src/southbridge/amd/cimx/sb900/late.c</span><br><span>@@ -25,8 +25,8 @@</span><br><span> #include <device/pci_ehci.h></span><br><span> #include <arch/acpi.h></span><br><span> #include "lpc.h" /* lpc_read_resources */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "SbPlatform.h" /* Platform Specific Definitions */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SbPlatform.h" /* Platform Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */</span><br><span> </span><br><span> #ifndef _RAMSTAGE_</span><br><span> #define _RAMSTAGE_</span><br><span>@@ -353,13 +353,13 @@</span><br><span> </span><br><span> case (0x11 << 3) | 0: /* 0:11.0 SATA */</span><br><span> if (dev->enabled) {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->SATAMODE.SataMode.SataController = ENABLED;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->SATAMODE.SataMode.SataController = ENABLED;</span><br><span> if (1 == sb_chip->boot_switch_sata_ide)</span><br><span> sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.</span><br><span> else if (0 == sb_chip->boot_switch_sata_ide)</span><br><span> sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->SATAMODE.SataMode.SataController = DISABLED;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->SATAMODE.SataMode.SataController = DISABLED;</span><br><span> }</span><br><span> </span><br><span> //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY</span><br><span>@@ -380,19 +380,19 @@</span><br><span> if (dev->enabled) {</span><br><span> sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;</span><br><span> }</span><br><span> //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY</span><br><span> break;</span><br><span> </span><br><span> case (0x14 << 3) | 2: /* 0:14:2 HDA */</span><br><span> if (dev->enabled) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (AZALIA_DISABLE == sb_config->AzaliaController) {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->AzaliaController = AZALIA_AUTO;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (AZALIA_DISABLE == sb_config->AzaliaController) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->AzaliaController = AZALIA_AUTO;</span><br><span> }</span><br><span> printk(BIOS_DEBUG, "hda enabled\n");</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- sb_config->AzaliaController = AZALIA_DISABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_config->AzaliaController = AZALIA_DISABLE;</span><br><span> printk(BIOS_DEBUG, "hda disabled\n");</span><br><span> }</span><br><span> //- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio</span><br><span>@@ -446,7 +446,7 @@</span><br><span> </span><br><span> /* Special setting ABCFG registers before PCI emulation. */</span><br><span> //- abSpecialSetBeforePciEnum(sb_config);</span><br><span style="color: hsl(0, 100%, 40%);">-//- usbDesertPll(sb_config);</span><br><span style="color: hsl(120, 100%, 40%);">+//- usbDesertPll(sb_config);</span><br><span> //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;</span><br><span> //AmdSbDispatcher(sb_config);</span><br><span> }</span><br><span>diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c</span><br><span>index 5f20c12..956994d 100644</span><br><span>--- a/src/southbridge/amd/cs5536/cs5536.c</span><br><span>+++ b/src/southbridge/amd/cs5536/cs5536.c</span><br><span>@@ -514,7 +514,7 @@</span><br><span> </span><br><span> /****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * ChipsetInit</span><br><span style="color: hsl(120, 100%, 40%);">+ * ChipsetInit</span><br><span> *</span><br><span> * Called from northbridge init (Pre-VSA).</span><br><span> *</span><br><span>diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h</span><br><span>index 72dbd5c..1707a8e 100644</span><br><span>--- a/src/southbridge/amd/cs5536/cs5536.h</span><br><span>+++ b/src/southbridge/amd/cs5536/cs5536.h</span><br><span>@@ -413,7 +413,7 @@</span><br><span> </span><br><span> /* FLASH device macros */</span><br><span> #define FLASH_TYPE_NONE 0 /* No flash device installed */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_TYPE_NAND 1 /* NAND device */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FLASH_TYPE_NAND 1 /* NAND device */</span><br><span> #define FLASH_TYPE_NOR 2 /* NOR device */</span><br><span> </span><br><span> #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h</span><br><span>index 679f233..408ff01 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h</span><br><span>+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h</span><br><span>@@ -46,7 +46,7 @@</span><br><span> #define PIRQ_FC 0x14 /* FC */</span><br><span> #define PIRQ_GEC 0x15 /* GEC */</span><br><span> #define PIRQ_PMON 0x16 /* Performance Monitor */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQ_SD 0x17 /* SD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_SD 0x17 /* SD */</span><br><span> #define PIRQ_IMC0 0x20 /* IMC INT0 */</span><br><span> #define PIRQ_IMC1 0x21 /* IMC INT1 */</span><br><span> #define PIRQ_IMC2 0x22 /* IMC INT2 */</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>index d95385b..b5a86dc 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>@@ -163,7 +163,7 @@</span><br><span> tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE);</span><br><span> tmp |= alt_wideio_enable[port];</span><br><span> pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp);</span><br><span style="color: hsl(0, 100%, 40%);">- } else { /* 512 */</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* 512 */</span><br><span> tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE);</span><br><span> tmp &= ~alt_wideio_enable[port];</span><br><span> pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp);</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>index 091464f..922c608 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>+++ b/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>@@ -121,7 +121,7 @@</span><br><span> </span><br><span> #define LPC_WIDEIO2_GENERIC_PORT 0x90</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CNTRL0 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CNTRL0 0x00</span><br><span> #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))</span><br><span> /* Nominal is 16.7MHz on older devices, 33MHz on newer */</span><br><span> #define SPI_READ_MODE_NOM 0x00000000</span><br><span>@@ -137,7 +137,7 @@</span><br><span> </span><br><span> #define SPI_CNTRL1 0x0c</span><br><span> /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))</span><br><span> #define SPI_NORM_SPEED_SH 12</span><br><span> #define SPI_FAST_SPEED_SH 8</span><br><span> </span><br><span>@@ -153,10 +153,10 @@</span><br><span> #define SPI_SPEED_800K (BIT(2) | BIT(0))</span><br><span> #define SPI_NORM_SPEED_NEW_SH 12</span><br><span> #define SPI_FAST_SPEED_NEW_SH 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_ALT_SPEED_NEW_SH 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_ALT_SPEED_NEW_SH 4</span><br><span> #define SPI_TPM_SPEED_NEW_SH 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI100_HOST_PREF_CONFIG 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI100_HOST_PREF_CONFIG 0x2c</span><br><span> #define SPI_RD4DW_EN_HOST BIT(15)</span><br><span> </span><br><span> static inline int hudson_sata_enable(void)</span><br><span>diff --git a/src/southbridge/amd/rs690/early_setup.c b/src/southbridge/amd/rs690/early_setup.c</span><br><span>index 7746fca..e2f54cc 100644</span><br><span>--- a/src/southbridge/amd/rs690/early_setup.c</span><br><span>+++ b/src/southbridge/amd/rs690/early_setup.c</span><br><span>@@ -17,7 +17,7 @@</span><br><span> </span><br><span> #define NBHTIU_INDEX 0xA8</span><br><span> #define NBMISC_INDEX 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMC_INDEX 0xE8</span><br><span> </span><br><span> static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)</span><br><span> {</span><br><span>diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c</span><br><span>index c45e621d..52886ee 100644</span><br><span>--- a/src/southbridge/amd/rs690/gfx.c</span><br><span>+++ b/src/southbridge/amd/rs690/gfx.c</span><br><span>@@ -348,8 +348,8 @@</span><br><span> </span><br><span> /* For single port GFX configuration Only</span><br><span> * width:</span><br><span style="color: hsl(0, 100%, 40%);">-* 000 = x16</span><br><span style="color: hsl(0, 100%, 40%);">-* 001 = x1</span><br><span style="color: hsl(120, 100%, 40%);">+* 000 = x16</span><br><span style="color: hsl(120, 100%, 40%);">+* 001 = x1</span><br><span> * 010 = x2</span><br><span> * 011 = x4</span><br><span> * 100 = x8</span><br><span>diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c</span><br><span>index 2e888cd..3ba08b6 100644</span><br><span>--- a/src/southbridge/amd/rs690/rs690.c</span><br><span>+++ b/src/southbridge/amd/rs690/rs690.c</span><br><span>@@ -89,7 +89,7 @@</span><br><span> byte |= 1 << 0;</span><br><span> pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */</span><br><span> /* TODO: */</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h</span><br><span>index 7fde16f..819244b3 100644</span><br><span>--- a/src/southbridge/amd/rs690/rs690.h</span><br><span>+++ b/src/southbridge/amd/rs690/rs690.h</span><br><span>@@ -20,10 +20,10 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMISC_INDEX 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBHTIU_INDEX 0xA8</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBPCIE_INDEX 0xE0</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMISC_INDEX 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBHTIU_INDEX 0xA8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBPCIE_INDEX 0xE0</span><br><span> #define EXT_CONF_BASE_ADDRESS 0xE0000000</span><br><span> #define TEMP_MMIO_BASE_ADDRESS 0xC0000000</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c</span><br><span>index 7bc9435..ab75e5f 100644</span><br><span>--- a/src/southbridge/amd/rs780/early_setup.c</span><br><span>+++ b/src/southbridge/amd/rs780/early_setup.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */</span><br><span> #define NBMISC_INDEX 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMC_INDEX 0xE8</span><br><span> </span><br><span> static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)</span><br><span> {</span><br><span>diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c</span><br><span>index 79a9db7..4cf966d 100644</span><br><span>--- a/src/southbridge/amd/rs780/gfx.c</span><br><span>+++ b/src/southbridge/amd/rs780/gfx.c</span><br><span>@@ -189,7 +189,7 @@</span><br><span> printk(BIOS_DEBUG, "Dev ID %x\n", Value);</span><br><span> if ((Value & 0xffff) == 0x1102) {//Creative</span><br><span> //Found Creative SB</span><br><span style="color: hsl(0, 100%, 40%);">- u32 MMIOStart = 0xffffffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 MMIOStart = 0xffffffff;</span><br><span> u32 MMIOLimit = 0;</span><br><span> for (Reg = 0x10; Reg < 0x20; Reg+=4) {</span><br><span> u32 BaseA, LimitA;</span><br><span>@@ -452,7 +452,7 @@</span><br><span> vgainfo.ulMinSidePortClock = 333*100;</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default</span><br><span style="color: hsl(120, 100%, 40%);">+ vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default</span><br><span> </span><br><span> // find the DDR memory frequency</span><br><span> if (is_family10h()) {</span><br><span>@@ -1112,8 +1112,8 @@</span><br><span> </span><br><span> /* For single port GFX configuration Only</span><br><span> * width:</span><br><span style="color: hsl(0, 100%, 40%);">-* 000 = x16</span><br><span style="color: hsl(0, 100%, 40%);">-* 001 = x1</span><br><span style="color: hsl(120, 100%, 40%);">+* 000 = x16</span><br><span style="color: hsl(120, 100%, 40%);">+* 001 = x1</span><br><span> * 010 = x2</span><br><span> * 011 = x4</span><br><span> * 100 = x8</span><br><span>diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c</span><br><span>index ef40ffd..f4f33ef 100644</span><br><span>--- a/src/southbridge/amd/rs780/rs780.c</span><br><span>+++ b/src/southbridge/amd/rs780/rs780.c</span><br><span>@@ -93,7 +93,7 @@</span><br><span> byte |= 1 << 0;</span><br><span> pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */</span><br><span> /* TODO: */</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h</span><br><span>index 971637b..fdc67a4 100644</span><br><span>--- a/src/southbridge/amd/rs780/rs780.h</span><br><span>+++ b/src/southbridge/amd/rs780/rs780.h</span><br><span>@@ -22,10 +22,10 @@</span><br><span> #include "chip.h"</span><br><span> #include "rev.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMISC_INDEX 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBHTIU_INDEX 0x94</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBPCIE_INDEX 0xE0</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMISC_INDEX 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBHTIU_INDEX 0x94</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBPCIE_INDEX 0xE0</span><br><span> #define EXT_CONF_BASE_ADDRESS 0xE0000000</span><br><span> #define TEMP_MMIO_BASE_ADDRESS 0xC0000000</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c</span><br><span>index f68bfd5..75bed17 100644</span><br><span>--- a/src/southbridge/amd/sb600/early_setup.c</span><br><span>+++ b/src/southbridge/amd/sb600/early_setup.c</span><br><span>@@ -57,7 +57,7 @@</span><br><span> * If you use FWH ROMs, you have to setup IDSEL.</span><br><span> * Reviewed-by: Carl-Daniel Hailfinger</span><br><span> * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1</span><br><span style="color: hsl(0, 100%, 40%);">-* (LPC ISA Bridge)</span><br><span style="color: hsl(120, 100%, 40%);">+* (LPC ISA Bridge)</span><br><span> ***************************************/</span><br><span> static void sb600_lpc_init(void)</span><br><span> {</span><br><span>diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c</span><br><span>index 436854e..14b28cc 100644</span><br><span>--- a/src/southbridge/amd/sb700/sm.c</span><br><span>+++ b/src/southbridge/amd/sb700/sm.c</span><br><span>@@ -225,7 +225,7 @@</span><br><span> pci_write_config8(dev, 0xE1, byte);</span><br><span> </span><br><span> /* 2.5 Enabling Non-Posted Memory Write */</span><br><span style="color: hsl(0, 100%, 40%);">- axindxc_reg(0x10, 1 << 9, 1 << 9);</span><br><span style="color: hsl(120, 100%, 40%);">+ axindxc_reg(0x10, 1 << 9, 1 << 9);</span><br><span> </span><br><span> /* 2.11 IO Trap Settings */</span><br><span> abcfg_reg(0x10090, 1 << 16, 1 << 16);</span><br><span>diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c</span><br><span>index 12b9dd6..bf79056 100644</span><br><span>--- a/src/southbridge/amd/sb700/usb.c</span><br><span>+++ b/src/southbridge/amd/sb700/usb.c</span><br><span>@@ -215,14 +215,14 @@</span><br><span> /* the pci id of usb ctrl 0 and 1 are the same. */</span><br><span> /*</span><br><span> * static const struct pci_driver usb_3_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- * .ops = &usb_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(0, 100%, 40%);">- * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .ops = &usb_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0,</span><br><span> * };</span><br><span> * static const struct pci_driver usb_4_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- * .ops = &usb_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(0, 100%, 40%);">- * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .ops = &usb_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1,</span><br><span> * };</span><br><span> */</span><br><span> </span><br><span>@@ -248,8 +248,8 @@</span><br><span> };</span><br><span> /*</span><br><span> * static const struct pci_driver usb_5_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- * .ops = &usb_ops2,</span><br><span style="color: hsl(0, 100%, 40%);">- * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(0, 100%, 40%);">- * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .ops = &usb_ops2,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2,</span><br><span> * };</span><br><span> */</span><br><span>diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c</span><br><span>index 2318a8f..715095f 100644</span><br><span>--- a/src/southbridge/amd/sb800/usb.c</span><br><span>+++ b/src/southbridge/amd/sb800/usb.c</span><br><span>@@ -166,14 +166,14 @@</span><br><span> /* the pci id of usb ctrl 0 and 1 are the same. */</span><br><span> /*</span><br><span> * static const struct pci_driver usb_3_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- * .ops = &usb_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(0, 100%, 40%);">- * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .ops = &usb_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0,</span><br><span> * };</span><br><span> * static const struct pci_driver usb_4_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- * .ops = &usb_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(0, 100%, 40%);">- * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .ops = &usb_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1,</span><br><span> * };</span><br><span> */</span><br><span> </span><br><span>@@ -199,8 +199,8 @@</span><br><span> };</span><br><span> /*</span><br><span> * static const struct pci_driver usb_5_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- * .ops = &usb_ops2,</span><br><span style="color: hsl(0, 100%, 40%);">- * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(0, 100%, 40%);">- * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .ops = &usb_ops2,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .vendor = PCI_VENDOR_ID_ATI,</span><br><span style="color: hsl(120, 100%, 40%);">+ * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2,</span><br><span> * };</span><br><span> */</span><br><span>diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h</span><br><span>index 0c0fd29..5c55356 100644</span><br><span>--- a/src/southbridge/amd/sr5650/cmn.h</span><br><span>+++ b/src/southbridge/amd/sr5650/cmn.h</span><br><span>@@ -19,12 +19,12 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMISC_INDEX 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(0, 100%, 40%);">-#define NBPCIE_INDEX 0xE0</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2CFG_INDEX 0xF0</span><br><span style="color: hsl(0, 100%, 40%);">-#define L1CFG_INDEX 0xF8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMISC_INDEX 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBMC_INDEX 0xE8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NBPCIE_INDEX 0xE0</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2CFG_INDEX 0xF0</span><br><span style="color: hsl(120, 100%, 40%);">+#define L1CFG_INDEX 0xF8</span><br><span> #define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS</span><br><span> #define TEMP_MMIO_BASE_ADDRESS 0xC0000000</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c</span><br><span>index 9e2bd92..8986e67 100644</span><br><span>--- a/src/southbridge/amd/sr5650/pcie.c</span><br><span>+++ b/src/southbridge/amd/sr5650/pcie.c</span><br><span>@@ -454,14 +454,14 @@</span><br><span> reg = 0xE8;</span><br><span> port = dev->path.pci.devfn >> 3;</span><br><span> switch (port) {</span><br><span style="color: hsl(0, 100%, 40%);">- //PCIE_CORE_INDEX_GPP1</span><br><span style="color: hsl(120, 100%, 40%);">+ //PCIE_CORE_INDEX_GPP1</span><br><span> case 2:</span><br><span> case 3:</span><br><span> reg = 0x94;</span><br><span> mask = 1 << 16;</span><br><span> break;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- //PCIE_CORE_INDEX_GPP2</span><br><span style="color: hsl(120, 100%, 40%);">+ //PCIE_CORE_INDEX_GPP2</span><br><span> case 11:</span><br><span> case 12:</span><br><span> value = 1 << 28;</span><br><span>@@ -479,7 +479,7 @@</span><br><span> value = 1 << 25;</span><br><span> break;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- //PCIE_CORE_INDEX_SB;</span><br><span style="color: hsl(120, 100%, 40%);">+ //PCIE_CORE_INDEX_SB;</span><br><span> case 8:</span><br><span> reg = 0x94;</span><br><span> mask = 1 << 24;</span><br><span>diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>index ec78467..24a4c82 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.c</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>@@ -430,7 +430,7 @@</span><br><span> dword |= (0x1 << 0);</span><br><span> l2cfg_ind_write_index(nb_dev, 0x44, dword);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// if (get_nb_rev(nb_dev) == REV_SR5650_A21) {</span><br><span style="color: hsl(120, 100%, 40%);">+// if (get_nb_rev(nb_dev) == REV_SR5650_A21) {</span><br><span> dword = l2cfg_ind_read_index(nb_dev, 0x7);</span><br><span> dword |= (0x1 << 1);</span><br><span> l2cfg_ind_write_index(nb_dev, 0x7, dword);</span><br><span>@@ -482,7 +482,7 @@</span><br><span> dword = l2cfg_ind_read_index(nb_dev, 0x6);</span><br><span> dword |= (0x1 << 8);</span><br><span> l2cfg_ind_write_index(nb_dev, 0x6, dword);</span><br><span style="color: hsl(0, 100%, 40%);">-// }</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span> </span><br><span> l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002);</span><br><span> </span><br><span>diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c</span><br><span>index b10c23f..8619cbd 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/lpc.c</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/lpc.c</span><br><span>@@ -89,7 +89,7 @@</span><br><span> case 0x64:</span><br><span> reg |= (1<<29); break;</span><br><span> case 0x3f8: // COM1</span><br><span style="color: hsl(0, 100%, 40%);">- reg |= (1<<6); break;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg |= (1<<6); break;</span><br><span> case 0x2f8: // COM2</span><br><span> reg |= (1<<7); break;</span><br><span> case 0x378: // Parallel 1</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl</span><br><span>index cfa27d2..736c60a 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl</span><br><span>+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl</span><br><span>@@ -202,7 +202,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h</span><br><span>index f95a0b4..b0f2a6e 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me.h</span><br><span>@@ -292,7 +292,7 @@</span><br><span> typedef struct {</span><br><span> u16 lock_state : 1;</span><br><span> u16 authenticate_module : 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 s3authentication : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 s3authentication : 1;</span><br><span> u16 flash_wear_out : 1;</span><br><span> u16 flash_variable_security : 1;</span><br><span> u16 wwan3gpresent : 1;</span><br><span>@@ -350,7 +350,7 @@</span><br><span> typedef struct {</span><br><span> u32 mbp_size : 8;</span><br><span> u32 num_entries : 8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rsvd : 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsvd : 16;</span><br><span> } __packed mbp_header;</span><br><span> </span><br><span> typedef struct {</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>index e2ff851e..622153c 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>@@ -188,7 +188,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c</span><br><span>index d591bcc..ea48d9e 100644</span><br><span>--- a/src/southbridge/intel/common/pciehp.c</span><br><span>+++ b/src/southbridge/intel/common/pciehp.c</span><br><span>@@ -46,11 +46,11 @@</span><br><span> /*</span><br><span> Device (SLOT)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_ADR, 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_RMV, 0, NotSerialized)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (0x01)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_RMV, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c</span><br><span>index 99608dc..de4ff91 100644</span><br><span>--- a/src/southbridge/intel/common/smbus.c</span><br><span>+++ b/src/southbridge/intel/common/smbus.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> #define SMBHSTSTS_HOST_BUSY (1 << 0)</span><br><span> </span><br><span> #define SMBUS_TIMEOUT (10 * 1000 * 100)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMBUS_BLOCK_MAXLEN 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_BLOCK_MAXLEN 32</span><br><span> </span><br><span> static void smbus_delay(void)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl</span><br><span>index 114aea6..5107491 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl</span><br><span>@@ -202,7 +202,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h</span><br><span>index f95a0b4..b0f2a6e 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/me.h</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/me.h</span><br><span>@@ -292,7 +292,7 @@</span><br><span> typedef struct {</span><br><span> u16 lock_state : 1;</span><br><span> u16 authenticate_module : 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 s3authentication : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 s3authentication : 1;</span><br><span> u16 flash_wear_out : 1;</span><br><span> u16 flash_variable_security : 1;</span><br><span> u16 wwan3gpresent : 1;</span><br><span>@@ -350,7 +350,7 @@</span><br><span> typedef struct {</span><br><span> u32 mbp_size : 8;</span><br><span> u32 num_entries : 8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rsvd : 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsvd : 16;</span><br><span> } __packed mbp_header;</span><br><span> </span><br><span> typedef struct {</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c</span><br><span>index 14637e6..2248904 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/smi.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c</span><br><span>@@ -324,7 +324,7 @@</span><br><span> reset_pm1_status();</span><br><span> </span><br><span> /* Set EOS bit so other SMIs can occur. */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_set_eos();</span><br><span style="color: hsl(120, 100%, 40%);">+ smi_set_eos();</span><br><span> }</span><br><span> </span><br><span> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c</span><br><span>index 83eab79..e873792 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c</span><br><span>@@ -659,7 +659,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/acpi/pch.asl b/src/southbridge/intel/fsp_i89xx/acpi/pch.asl</span><br><span>index f2015d3..7036f33 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/acpi/pch.asl</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/acpi/pch.asl</span><br><span>@@ -202,7 +202,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/me.h b/src/southbridge/intel/fsp_i89xx/me.h</span><br><span>index f95a0b4..b0f2a6e 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/me.h</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/me.h</span><br><span>@@ -292,7 +292,7 @@</span><br><span> typedef struct {</span><br><span> u16 lock_state : 1;</span><br><span> u16 authenticate_module : 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 s3authentication : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 s3authentication : 1;</span><br><span> u16 flash_wear_out : 1;</span><br><span> u16 flash_variable_security : 1;</span><br><span> u16 wwan3gpresent : 1;</span><br><span>@@ -350,7 +350,7 @@</span><br><span> typedef struct {</span><br><span> u32 mbp_size : 8;</span><br><span> u32 num_entries : 8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rsvd : 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsvd : 16;</span><br><span> } __packed mbp_header;</span><br><span> </span><br><span> typedef struct {</span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c</span><br><span>index 3658a82..0ef7ba8 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/smihandler.c</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c</span><br><span>@@ -659,7 +659,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl</span><br><span>index 696a81a..b55bd92 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl</span><br><span>@@ -208,7 +208,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c</span><br><span>index 3a08daa..b2b4662 100644</span><br><span>--- a/src/southbridge/intel/i82801dx/smihandler.c</span><br><span>+++ b/src/southbridge/intel/i82801dx/smihandler.c</span><br><span>@@ -542,7 +542,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl</span><br><span>index 8a9aff4..cf158df 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl</span><br><span>+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl</span><br><span>@@ -129,7 +129,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl</span><br><span>index 143ecb1..52b263f 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/acpi/ich9.asl</span><br><span>+++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl</span><br><span>@@ -132,7 +132,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>index 7ad00ed..96337ef 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>@@ -402,7 +402,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl</span><br><span>index da8b789..985e8b6 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/acpi/ich10.asl</span><br><span>+++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl</span><br><span>@@ -132,7 +132,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c</span><br><span>index 35e79c6..f4382d7 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/smihandler.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/smihandler.c</span><br><span>@@ -402,7 +402,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h</span><br><span>index b576cc1..6f1dfe7 100644</span><br><span>--- a/src/southbridge/intel/i82870/82870.h</span><br><span>+++ b/src/southbridge/intel/i82870/82870.h</span><br><span>@@ -3,9 +3,9 @@</span><br><span> #define ABAR 0x40</span><br><span> </span><br><span> /* for pci bridge 1460 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MTT 0x042</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCCR 0x0f0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ACNF 0x0e0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MTT 0x042</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCCR 0x0f0</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACNF 0x0e0</span><br><span> #define STRP 0x44 // Strap status register</span><br><span> </span><br><span> #define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN)</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h</span><br><span>index d62b22a..6423d8d 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/me.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/me.h</span><br><span>@@ -191,7 +191,7 @@</span><br><span> #define MKHI_MDES_ENABLE 0x09</span><br><span> </span><br><span> #define MKHI_GET_FW_VERSION 0x02</span><br><span style="color: hsl(0, 100%, 40%);">-#define MKHI_SET_UMA 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define MKHI_SET_UMA 0x08</span><br><span> #define MKHI_END_OF_POST 0x0c</span><br><span> #define MKHI_FEATURE_OVERRIDE 0x14</span><br><span> </span><br><span>@@ -293,7 +293,7 @@</span><br><span> typedef struct {</span><br><span> u16 lock_state : 1;</span><br><span> u16 authenticate_module : 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 s3authentication : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 s3authentication : 1;</span><br><span> u16 flash_wear_out : 1;</span><br><span> u16 flash_variable_security : 1;</span><br><span> u16 wwan3gpresent : 1;</span><br><span>@@ -351,7 +351,7 @@</span><br><span> typedef struct {</span><br><span> u32 mbp_size : 8;</span><br><span> u32 num_entries : 8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rsvd : 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsvd : 16;</span><br><span> } __packed mbp_header;</span><br><span> </span><br><span> typedef struct {</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c</span><br><span>index 9f6badb..10e2fa6 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smi.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smi.c</span><br><span>@@ -325,7 +325,7 @@</span><br><span> reset_pm1_status();</span><br><span> </span><br><span> /* Set EOS bit so other SMIs can occur. */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_set_eos();</span><br><span style="color: hsl(120, 100%, 40%);">+ smi_set_eos();</span><br><span> }</span><br><span> </span><br><span> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>index 12a7ac0..dd36718 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>@@ -762,7 +762,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl</span><br><span>index fbbd26d..eaa2690 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl</span><br><span>+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl</span><br><span>@@ -45,7 +45,7 @@</span><br><span> Offset(0x1000), // Chipset</span><br><span> Offset(0x3000), // Legacy Configuration Registers</span><br><span> Offset(0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> Offset(0x3418), // FD (Function Disable)</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h</span><br><span>index a1987eb..cef2e55 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/me.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/me.h</span><br><span>@@ -374,7 +374,7 @@</span><br><span> typedef struct {</span><br><span> u32 mbp_size : 8;</span><br><span> u32 num_entries : 8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rsvd : 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsvd : 16;</span><br><span> } __packed mbp_header;</span><br><span> </span><br><span> typedef struct {</span><br><span>@@ -459,7 +459,7 @@</span><br><span> typedef struct {</span><br><span> u16 lock_state : 1;</span><br><span> u16 authenticate_module : 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 s3authentication : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 s3authentication : 1;</span><br><span> u16 flash_wear_out : 1;</span><br><span> u16 flash_variable_security : 1;</span><br><span> u16 reserved : 11;</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>index 70f2834..ae996e8 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>@@ -392,8 +392,8 @@</span><br><span> #define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */</span><br><span> #define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */</span><br><span> #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */</span><br><span style="color: hsl(0, 100%, 40%);">-#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */</span><br><span style="color: hsl(0, 100%, 40%);">-#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */</span><br><span style="color: hsl(120, 100%, 40%);">+#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */</span><br><span> #define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */</span><br><span> #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */</span><br><span> #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>index dcec3f0..2ab4a46 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>@@ -450,7 +450,7 @@</span><br><span> data = RCBA32(0x1e18);</span><br><span> data &= mask;</span><br><span> // if (smi1)</span><br><span style="color: hsl(0, 100%, 40%);">- // southbridge_smi_command(data);</span><br><span style="color: hsl(120, 100%, 40%);">+ // southbridge_smi_command(data);</span><br><span> // return;</span><br><span> }</span><br><span> // Fall through to debug</span><br><span>diff --git a/src/southbridge/via/common/early_smbus_print_error.c b/src/southbridge/via/common/early_smbus_print_error.c</span><br><span>index 842c5d6..1aafcf3 100644</span><br><span>--- a/src/southbridge/via/common/early_smbus_print_error.c</span><br><span>+++ b/src/southbridge/via/common/early_smbus_print_error.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> * a transaction is processed.</span><br><span> * @param loops The number of times a transaction was attempted.</span><br><span> * @return 0 if no error occurred</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 if an error was detected</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 if an error was detected</span><br><span> */</span><br><span> int smbus_print_error(u32 smbus_dev, u8 host_status, int loops)</span><br><span> {</span><br><span>diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c</span><br><span>index f7ccd75..3775fbc 100644</span><br><span>--- a/src/southbridge/via/k8t890/bridge.c</span><br><span>+++ b/src/southbridge/via/k8t890/bridge.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span> writeback(dev, 0x42, 0x80);</span><br><span> writeback(dev, 0x44, 0x35);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet</span><br><span style="color: hsl(120, 100%, 40%);">+ writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet</span><br><span> * says it is reserved</span><br><span> */</span><br><span> #endif</span><br><span>diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c</span><br><span>index 61fa28e..8ec4df7 100644</span><br><span>--- a/src/southbridge/via/k8t890/ctrl.c</span><br><span>+++ b/src/southbridge/via/k8t890/ctrl.c</span><br><span>@@ -104,7 +104,7 @@</span><br><span> * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88</span><br><span> * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01</span><br><span> * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11</span><br><span style="color: hsl(0, 100%, 40%);">- * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98</span><br><span style="color: hsl(120, 100%, 40%);">+ * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98</span><br><span> * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77</span><br><span> * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11</span><br><span> * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01</span><br><span>diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c</span><br><span>index 1f126cc..80f6e01 100644</span><br><span>--- a/src/southbridge/via/k8t890/dram.c</span><br><span>+++ b/src/southbridge/via/k8t890/dram.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> if (ret) {</span><br><span> printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret);</span><br><span> fbbits = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> if ((fbbits < 1) || (fbbits > 7)) {</span><br><span> printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n",</span><br><span>diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c</span><br><span>index 3257cc2..f8d1d84 100644</span><br><span>--- a/src/southbridge/via/vt8237r/early_smbus.c</span><br><span>+++ b/src/southbridge/via/vt8237r/early_smbus.c</span><br><span>@@ -384,17 +384,17 @@</span><br><span> #if defined(__GNUC__)</span><br><span> /*</span><br><span> * Offset 0x58:</span><br><span style="color: hsl(0, 100%, 40%);">- * 31:20 reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 31:20 reserved</span><br><span> * 19:16 4 bit position in shadow EEPROM</span><br><span> * 15:0 data to write</span><br><span> *</span><br><span> * Offset 0x5c:</span><br><span> * 31:28 reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * 27 ERDBG - enable read from 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+ * 27 ERDBG - enable read from 0x5c</span><br><span> * 26 reserved</span><br><span> * 25 SEELD</span><br><span> * 24 SEEPR - write 1 when done updating, wait until SEELD is</span><br><span style="color: hsl(0, 100%, 40%);">- * set to 1, sticky</span><br><span style="color: hsl(120, 100%, 40%);">+ * set to 1, sticky</span><br><span> * cleared by reset, if it is 1 writing is disabled</span><br><span> * 19:16 4 bit position in shadow EEPROM</span><br><span> * 15:0 data from shadow EEPROM</span><br><span>diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c</span><br><span>index 46b1e23..c2bece2 100644</span><br><span>--- a/src/southbridge/via/vt8237r/lpc.c</span><br><span>+++ b/src/southbridge/via/vt8237r/lpc.c</span><br><span>@@ -524,7 +524,7 @@</span><br><span> pci_write_config8(dev, 0x4c, 0x44);</span><br><span> </span><br><span> /* ROM memory cycles go to LPC. */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, 0x59, 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0x59, 0x80);</span><br><span> </span><br><span> /*</span><br><span> * Bit | Meaning</span><br><span>diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c</span><br><span>index aa60489..888d5c3 100644</span><br><span>--- a/src/southbridge/via/vt8237r/nic.c</span><br><span>+++ b/src/southbridge/via/vt8237r/nic.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span> res->gran = 8;</span><br><span> res->limit = res->base + res->size - 1;</span><br><span> res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |</span><br><span style="color: hsl(0, 100%, 40%);">- IORESOURCE_ASSIGNED;</span><br><span style="color: hsl(120, 100%, 40%);">+ IORESOURCE_ASSIGNED;</span><br><span> #else</span><br><span> pci_dev_read_resources(dev);</span><br><span> #endif</span><br><span>diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c</span><br><span>index 42a0afe..7e2e21c 100644</span><br><span>--- a/src/southbridge/via/vt8237r/usb.c</span><br><span>+++ b/src/southbridge/via/vt8237r/usb.c</span><br><span>@@ -82,7 +82,7 @@</span><br><span> res->align = 10;</span><br><span> res->gran = 8;</span><br><span> res->flags = IORESOURCE_IO | IORESOURCE_FIXED |</span><br><span style="color: hsl(0, 100%, 40%);">- IORESOURCE_ASSIGNED;</span><br><span style="color: hsl(120, 100%, 40%);">+ IORESOURCE_ASSIGNED;</span><br><span> #else</span><br><span> pci_dev_read_resources(dev);</span><br><span> #endif</span><br><span>@@ -147,7 +147,7 @@</span><br><span> res->gran = 8;</span><br><span> res->limit = res->base + res->size - 1;</span><br><span> res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |</span><br><span style="color: hsl(0, 100%, 40%);">- IORESOURCE_ASSIGNED;</span><br><span style="color: hsl(120, 100%, 40%);">+ IORESOURCE_ASSIGNED;</span><br><span> #else</span><br><span> pci_dev_read_resources(dev);</span><br><span> #endif</span><br><span>diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h</span><br><span>index f383736..ebf58da 100644</span><br><span>--- a/src/southbridge/via/vt8237r/vt8237r.h</span><br><span>+++ b/src/southbridge/via/vt8237r/vt8237r.h</span><br><span>@@ -84,7 +84,7 @@</span><br><span> #define SMBXMITADD (VT8237R_SMBUS_IO_BASE + 0x4)</span><br><span> #define SMBHSTDAT0 (VT8237R_SMBUS_IO_BASE + 0x5)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define HOST_RESET 0xff</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOST_RESET 0xff</span><br><span> /* 1 in the 0 bit of SMBHSTADD states to READ. */</span><br><span> #define READ_CMD 0x01</span><br><span> #define SMBUS_TIMEOUT (100 * 1000 * 10)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26604">change 26604</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26604"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9a2eada93f05b6a4adac3406c33b6e109b733324 </div>
<div style="display:none"> Gerrit-Change-Number: 26604 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>