<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26639">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">MB/tyan: Get rid of whitespace before tab<br><br>Change-Id: I19225ee52cd4ddf96cfecc3488d2114f6ae62b1a<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/tyan/s2912/resourcemap.c<br>M src/mainboard/tyan/s2912/romstage.c<br>M src/mainboard/tyan/s2912_fam10/resourcemap.c<br>3 files changed, 3 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/26639/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/tyan/s2912/resourcemap.c b/src/mainboard/tyan/s2912/resourcemap.c</span><br><span>index 9ac7ae4..2f8ec26 100644</span><br><span>--- a/src/mainboard/tyan/s2912/resourcemap.c</span><br><span>+++ b/src/mainboard/tyan/s2912/resourcemap.c</span><br><span>@@ -266,7 +266,7 @@</span><br><span>                *         This field defines the highest bus number in configuration region i</span><br><span>                */</span><br><span> //               PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */</span><br><span style="color: hsl(0, 100%, 40%);">-//             PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55       */</span><br><span style="color: hsl(120, 100%, 40%);">+//          PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55       */</span><br><span>           PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,</span><br><span>          PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,</span><br><span> </span><br><span>diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c</span><br><span>index 1650d3d..69d3d31 100644</span><br><span>--- a/src/mainboard/tyan/s2912/romstage.c</span><br><span>+++ b/src/mainboard/tyan/s2912/romstage.c</span><br><span>@@ -180,7 +180,7 @@</span><br><span>       // fidvid change will issue one LDTSTOP and the HT change will be effective too</span><br><span>      if (needs_reset) {</span><br><span>           printk(BIOS_INFO, "ht reset -\n");</span><br><span style="color: hsl(0, 100%, 40%);">-            soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+         soft_reset();</span><br><span>        }</span><br><span> </span><br><span>        allow_all_aps_stop(bsp_apicid);</span><br><span>diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c</span><br><span>index 14e3c53..bc03d21 100644</span><br><span>--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c</span><br><span>@@ -266,7 +266,7 @@</span><br><span>            *         This field defines the highest bus number in configuration region i</span><br><span>                */</span><br><span> //               PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */</span><br><span style="color: hsl(0, 100%, 40%);">-//              PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55        */</span><br><span style="color: hsl(120, 100%, 40%);">+//          PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55        */</span><br><span>           PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,</span><br><span>           PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26639">change 26639</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26639"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I19225ee52cd4ddf96cfecc3488d2114f6ae62b1a </div>
<div style="display:none"> Gerrit-Change-Number: 26639 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>