<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26637">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/supermicro: Get rid of whitespace before tab<br><br>Change-Id: Id2622e473959dcf105bfeeaebddd582593a3c274<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/supermicro/h8qme_fam10/romstage.c<br>M src/mainboard/supermicro/h8scm_fam10/devicetree.cb<br>M src/mainboard/supermicro/h8scm_fam10/dsdt.asl<br>3 files changed, 48 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/26637/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>index 723a665..f5222ed 100644</span><br><span>--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>@@ -294,8 +294,8 @@</span><br><span> </span><br><span> post_code(0x3D);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// printk(BIOS_DEBUG, "enable_smbus()\n");</span><br><span style="color: hsl(0, 100%, 40%);">-// enable_smbus(); /* enable in sio_setup */</span><br><span style="color: hsl(120, 100%, 40%);">+// printk(BIOS_DEBUG, "enable_smbus()\n");</span><br><span style="color: hsl(120, 100%, 40%);">+// enable_smbus(); /* enable in sio_setup */</span><br><span> </span><br><span> post_code(0x40);</span><br><span> </span><br><span>diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb</span><br><span>index 82229da9..d758157 100644</span><br><span>--- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb</span><br><span>+++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb</span><br><span>@@ -16,7 +16,7 @@</span><br><span> ##device pci 18.0 on end</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/sr5650</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 0.1 on end # CLKCONFIG</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 off end # PCIE P2P bridge 0x960b</span><br><span>@@ -44,49 +44,49 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on end # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # SM</span><br><span> device pci 14.1 on end # IDE 0x439c</span><br><span> device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec.</span><br><span> device pci 14.3 on # LPC 0x439d</span><br><span> chip superio/winbond/w83627hf</span><br><span> device pnp 2e.0 off # Floppy</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f0</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 6</span><br><span style="color: hsl(0, 100%, 40%);">- drq 0x74 = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 2</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.1 off # Parallel Port</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x378</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 off # Parallel Port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.2 off # Com1</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 off # Com1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.3 off # Com2</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x2f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off # Com2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.5 on # Keyboard</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x60</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x62 = 0x64</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span> irq 0x72 = 12</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.6 off # SFI</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x62 = 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off # SFI</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x100</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.7 off # GPIO_GAME_MIDI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off # GPIO_GAME_MIDI</span><br><span> io 0x60 = 0x220</span><br><span> io 0x62 = 0x300</span><br><span> irq 0x70 = 9</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.8 off end # WDTO_PLED</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.9 off end # GPIO_SUSLED</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.a off end # ACPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDTO_PLED</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off end # GPIO_SUSLED</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span> irq 0x70 = 5</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span> end #superio/winbond/w83627hf</span><br><span> end #LPC</span><br><span> device pci 14.4 on end # PCI 0x4384</span><br><span>diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl</span><br><span>index 1599767..67c27bf 100644</span><br><span>--- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl</span><br><span>+++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl</span><br><span>@@ -257,9 +257,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -855,7 +855,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -871,13 +871,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1044,7 +1044,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1067,19 +1067,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1091,7 +1091,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1108,7 +1108,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1139,7 +1139,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1149,7 +1149,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1557,7 +1557,7 @@</span><br><span> </span><br><span> #if 0</span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1690,7 +1690,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26637">change 26637</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id2622e473959dcf105bfeeaebddd582593a3c274 </div>
<div style="display:none"> Gerrit-Change-Number: 26637 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>