<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26610">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/asus: Get rid of whitespace before tab<br><br>Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/asus/am1i-a/dsdt.asl<br>M src/mainboard/asus/f2a85-m/acpi/gpe.asl<br>M src/mainboard/asus/f2a85-m/acpi/sleep.asl<br>M src/mainboard/asus/f2a85-m/buildOpts.c<br>M src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl<br>M src/mainboard/asus/kcma-d8/dsdt.asl<br>M src/mainboard/asus/kcma-d8/resourcemap.c<br>M src/mainboard/asus/kcma-d8/romstage.c<br>M src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl<br>M src/mainboard/asus/kfsn4-dre/dsdt.asl<br>M src/mainboard/asus/kfsn4-dre/resourcemap.c<br>M src/mainboard/asus/kfsn4-dre/romstage.c<br>M src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl<br>M src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c<br>M src/mainboard/asus/kfsn4-dre_k8/dsdt.asl<br>M src/mainboard/asus/kfsn4-dre_k8/resourcemap.c<br>M src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl<br>M src/mainboard/asus/kgpe-d16/dsdt.asl<br>M src/mainboard/asus/kgpe-d16/resourcemap.c<br>M src/mainboard/asus/kgpe-d16/romstage.c<br>M src/mainboard/asus/m2v-mx_se/dsdt.asl<br>M src/mainboard/asus/m4a78-em/devicetree.cb<br>M src/mainboard/asus/m4a78-em/dsdt.asl<br>M src/mainboard/asus/m4a785-m/devicetree.cb<br>M src/mainboard/asus/m4a785-m/dsdt.asl<br>M src/mainboard/asus/m4a785t-m/devicetree.cb<br>M src/mainboard/asus/m4a785t-m/dsdt.asl<br>M src/mainboard/asus/m5a88-v/devicetree.cb<br>M src/mainboard/asus/m5a88-v/dsdt.asl<br>29 files changed, 113 insertions(+), 113 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/26610/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl</span><br><span>index 4d91b2a..94f83ec 100644</span><br><span>--- a/src/mainboard/asus/am1i-a/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/am1i-a/dsdt.asl</span><br><span>@@ -45,7 +45,7 @@</span><br><span> </span><br><span> /* System Bus */</span><br><span> Scope(\_SB) { /* Start \_SB scope */</span><br><span style="color: hsl(0, 100%, 40%);">- /* global utility methods expected within the \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global utility methods expected within the \_SB scope */</span><br><span> #include <arch/x86/acpi/globutil.asl></span><br><span> </span><br><span> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */</span><br><span>diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl</span><br><span>index c34faaf..297db37 100644</span><br><span>--- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl</span><br><span>@@ -69,4 +69,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/asus/f2a85-m/acpi/sleep.asl b/src/mainboard/asus/f2a85-m/acpi/sleep.asl</span><br><span>index 3250f5e..08b7de4 100644</span><br><span>--- a/src/mainboard/asus/f2a85-m/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/asus/f2a85-m/acpi/sleep.asl</span><br><span>@@ -44,7 +44,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c</span><br><span>index f840382..cf307e7 100644</span><br><span>--- a/src/mainboard/asus/f2a85-m/buildOpts.c</span><br><span>+++ b/src/mainboard/asus/f2a85-m/buildOpts.c</span><br><span>@@ -170,8 +170,8 @@</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED</span><br><span> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED</span><br><span style="color: hsl(0, 100%, 40%);">-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span> #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl</span><br><span>index c2757fa..ee49dae 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl</span><br><span>+++ b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl</span><br><span>@@ -129,9 +129,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl</span><br><span>index f1bc896..5754d7c 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kcma-d8/dsdt.asl</span><br><span>@@ -113,7 +113,7 @@</span><br><span> Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> /* Root of the bus hierarchy */</span><br><span> Scope (\_SB)</span><br><span>diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c</span><br><span>index 937f4b7..0de14ad 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kcma-d8/resourcemap.c</span><br><span>@@ -226,7 +226,7 @@</span><br><span> * This field defines the start of PCI I/O region n</span><br><span> * [31:25] Reserved</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span>@@ -481,7 +481,7 @@</span><br><span> * This field defines the start of PCI I/O region n</span><br><span> * [31:25] Reserved</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c</span><br><span>index 9b121d1..7e7d3c2 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/romstage.c</span><br><span>+++ b/src/mainboard/asus/kcma-d8/romstage.c</span><br><span>@@ -546,7 +546,7 @@</span><br><span> */</span><br><span> if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {</span><br><span> dump_spd_registers(&cpu[0]);</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smbus_registers();</span><br><span style="color: hsl(120, 100%, 40%);">+ dump_smbus_registers();</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl</span><br><span>index 0afb841..bde6fb6 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl</span><br><span>@@ -231,7 +231,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl</span><br><span>index 2f1e86a..575715c 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl</span><br><span>@@ -126,7 +126,7 @@</span><br><span> Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> /* Root of the bus hierarchy */</span><br><span> Scope (\_SB)</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c</span><br><span>index cfbade6..f4e549b 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c</span><br><span>@@ -226,7 +226,7 @@</span><br><span> * This field defines the start of PCI I/O region n</span><br><span> * [31:25] Reserved</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c</span><br><span>index 105dacf..21b0dc6 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/romstage.c</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/romstage.c</span><br><span>@@ -318,7 +318,7 @@</span><br><span> */</span><br><span> if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {</span><br><span> dump_spd_registers(&cpu[0]);</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smbus_registers();</span><br><span style="color: hsl(120, 100%, 40%);">+ dump_smbus_registers();</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl</span><br><span>index 0afb841..bde6fb6 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl</span><br><span>@@ -231,7 +231,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c b/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c</span><br><span>index 6061f89..66de664 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c</span><br><span>@@ -58,9 +58,9 @@</span><br><span> pci_write_config32(dev, 0x84, 0x00000001);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */</span><br><span style="color: hsl(0, 100%, 40%);">-// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(0, 100%, 40%);">-// current, 0, 0, 2, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */</span><br><span style="color: hsl(120, 100%, 40%);">+// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(120, 100%, 40%);">+// current, 0, 0, 2, 0);</span><br><span> /* IRQ9 */</span><br><span> current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span> current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl b/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl</span><br><span>index ce01a49..62adeaa 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl</span><br><span>@@ -126,7 +126,7 @@</span><br><span> Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> /* Root of the bus hierarchy */</span><br><span> Scope (\_SB)</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c</span><br><span>index cfbade6..f4e549b 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c</span><br><span>@@ -226,7 +226,7 @@</span><br><span> * This field defines the start of PCI I/O region n</span><br><span> * [31:25] Reserved</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl</span><br><span>index c2757fa..ee49dae 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl</span><br><span>@@ -129,9 +129,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl</span><br><span>index 6a25b4d..ab6547c 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/dsdt.asl</span><br><span>@@ -115,7 +115,7 @@</span><br><span> Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> /* Root of the bus hierarchy */</span><br><span> Scope (\_SB)</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c</span><br><span>index d1fcad7..dcd7f77 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c</span><br><span>@@ -226,7 +226,7 @@</span><br><span> * This field defines the start of PCI I/O region n</span><br><span> * [31:25] Reserved</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span>@@ -481,7 +481,7 @@</span><br><span> * This field defines the start of PCI I/O region n</span><br><span> * [31:25] Reserved</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>index 89b654f..449ed1c 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>@@ -587,7 +587,7 @@</span><br><span> */</span><br><span> if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {</span><br><span> dump_spd_registers(&cpu[0]);</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smbus_registers();</span><br><span style="color: hsl(120, 100%, 40%);">+ dump_smbus_registers();</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl</span><br><span>index 30ce550..8303e1e 100644</span><br><span>--- a/src/mainboard/asus/m2v-mx_se/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl</span><br><span>@@ -99,7 +99,7 @@</span><br><span> Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */</span><br><span> Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */</span><br><span> Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */</span><br><span style="color: hsl(0, 100%, 40%);">- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */</span><br><span> Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },</span><br><span> Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },</span><br><span> Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },</span><br><span>diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb</span><br><span>index e760c17..f336c2b 100644</span><br><span>--- a/src/mainboard/asus/m4a78-em/devicetree.cb</span><br><span>+++ b/src/mainboard/asus/m4a78-em/devicetree.cb</span><br><span>@@ -9,7 +9,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 on end # PCIE P2P bridge 0x960b</span><br><span>@@ -40,7 +40,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl</span><br><span>index be3e54d..82f2ad3 100644</span><br><span>--- a/src/mainboard/asus/m4a78-em/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/m4a78-em/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1520,7 +1520,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1634,7 +1634,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb</span><br><span>index 4549ead..9dc937c 100644</span><br><span>--- a/src/mainboard/asus/m4a785-m/devicetree.cb</span><br><span>+++ b/src/mainboard/asus/m4a785-m/devicetree.cb</span><br><span>@@ -9,7 +9,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 off end # PCIE P2P bridge 0x960b</span><br><span>@@ -40,7 +40,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl</span><br><span>index be3e54d..82f2ad3 100644</span><br><span>--- a/src/mainboard/asus/m4a785-m/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/m4a785-m/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1520,7 +1520,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1634,7 +1634,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb</span><br><span>index 9783989..6fce0f3 100644</span><br><span>--- a/src/mainboard/asus/m4a785t-m/devicetree.cb</span><br><span>+++ b/src/mainboard/asus/m4a785t-m/devicetree.cb</span><br><span>@@ -9,7 +9,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 5.0 on end # onboard VGA</span><br><span> end</span><br><span>@@ -42,7 +42,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl</span><br><span>index 8e42026..e63ad40 100644</span><br><span>--- a/src/mainboard/asus/m4a785t-m/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/m4a785t-m/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1505,7 +1505,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> /* memory space for PCI BARs below 4GB */</span><br><span> Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)</span><br><span> }) /* End Name(_SB.PCI0.CRES) */</span><br><span>@@ -1557,7 +1557,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb</span><br><span>index 65ddf30..d0efbdf 100644</span><br><span>--- a/src/mainboard/asus/m5a88-v/devicetree.cb</span><br><span>+++ b/src/mainboard/asus/m5a88-v/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9712</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 off end # PCIE P2P bridge 0x960b</span><br><span>diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl</span><br><span>index 6aff564..9b6f222 100644</span><br><span>--- a/src/mainboard/asus/m5a88-v/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/m5a88-v/dsdt.asl</span><br><span>@@ -234,9 +234,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -832,7 +832,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -847,13 +847,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1020,7 +1020,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1043,19 +1043,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1067,7 +1067,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1084,7 +1084,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1115,7 +1115,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1125,7 +1125,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1477,7 +1477,7 @@</span><br><span> )</span><br><span> #if 0</span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1607,7 +1607,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26610">change 26610</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26610"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212 </div>
<div style="display:none"> Gerrit-Change-Number: 26610 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>