<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26651">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc: Get rid of whitespace before tab<br><br>Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/amd/common/block/pi/heapmanager.c<br>M src/soc/broadcom/cygnus/Makefile.inc<br>M src/soc/broadcom/cygnus/ddr_init.c<br>M src/soc/intel/apollolake/exit_car_fsp.S<br>M src/soc/intel/baytrail/include/soc/gpio.h<br>M src/soc/intel/baytrail/include/soc/msr.h<br>M src/soc/intel/baytrail/include/soc/xhci.h<br>M src/soc/intel/baytrail/romstage/early_spi.c<br>M src/soc/intel/broadwell/acpi/pch.asl<br>M src/soc/intel/broadwell/acpi/pci_irqs.asl<br>M src/soc/intel/cannonlake/include/soc/pmc.h<br>M src/soc/intel/cannonlake/reset.c<br>M src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>M src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>M src/soc/intel/common/block/scs/sd.c<br>M src/soc/intel/denverton_ns/acpi/lpc.asl<br>M src/soc/intel/denverton_ns/exit_car_fsp.S<br>M src/soc/intel/fsp_baytrail/include/soc/gpio.h<br>M src/soc/intel/fsp_baytrail/include/soc/xhci.h<br>M src/soc/intel/skylake/lockdown.c<br>M src/soc/nvidia/tegra/types.h<br>M src/soc/nvidia/tegra124/display.c<br>M src/soc/nvidia/tegra124/include/soc/clk_rst.h<br>M src/soc/nvidia/tegra124/sor.c<br>M src/soc/nvidia/tegra210/include/soc/clk_rst.h<br>M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h<br>M src/soc/qualcomm/ipq806x/include/soc/iomap.h<br>M src/soc/qualcomm/ipq806x/usb.c<br>M src/soc/rockchip/rk3399/include/soc/mipi.h<br>29 files changed, 85 insertions(+), 85 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/26651/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c</span><br><span>index 4bf456a..a75a440 100644</span><br><span>--- a/src/soc/amd/common/block/pi/heapmanager.c</span><br><span>+++ b/src/soc/amd/common/block/pi/heapmanager.c</span><br><span>@@ -363,7 +363,7 @@</span><br><span> ConcatenateNodes(AllocNodePtr, NextNodePtr);</span><br><span> } else {</span><br><span> /*AllocNodePtr->NextNodeOffset =</span><br><span style="color: hsl(0, 100%, 40%);">- * FreedNodePtr->NextNodeOffset; */</span><br><span style="color: hsl(120, 100%, 40%);">+ * FreedNodePtr->NextNodeOffset; */</span><br><span> AllocNodePtr->NextNodeOffset = NextNodeOffset;</span><br><span> }</span><br><span> /*</span><br><span>diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc</span><br><span>index 9f0019d..cfbaaa7 100644</span><br><span>--- a/src/soc/broadcom/cygnus/Makefile.inc</span><br><span>+++ b/src/soc/broadcom/cygnus/Makefile.inc</span><br><span>@@ -84,7 +84,7 @@</span><br><span> # CustomerRevisionID; /* Customer Revision ID */</span><br><span> #</span><br><span> # SBIUsage /* Boot Image Usage */</span><br><span style="color: hsl(0, 100%, 40%);">-# NONE 0 /* All purposes */</span><br><span style="color: hsl(120, 100%, 40%);">+# NONE 0 /* All purposes */</span><br><span> # SLEEP 1</span><br><span> # DEEP_SLEEP 2</span><br><span> # EXCEPTION 4</span><br><span>diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>index c208457..ff5dc87 100644</span><br><span>--- a/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>+++ b/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>@@ -1638,7 +1638,7 @@</span><br><span> asm(</span><br><span> "movw r3, #0x4c64\n"</span><br><span> "movt r3, #0x0302\n"</span><br><span style="color: hsl(0, 100%, 40%);">- "ldr r5, [r3]\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ "ldr r5, [r3]\n"</span><br><span> "mov lr, #0\n"</span><br><span> "mov pc, r5\n");</span><br><span> #endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */</span><br><span>diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S</span><br><span>index 92289a0..fbf2d31 100644</span><br><span>--- a/src/soc/intel/apollolake/exit_car_fsp.S</span><br><span>+++ b/src/soc/intel/apollolake/exit_car_fsp.S</span><br><span>@@ -28,11 +28,11 @@</span><br><span> * caching settings are based on an 8MiB Flash Size given as a</span><br><span> * parameter to TempRamInit.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * TempRamExit MTRR Settings:</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x100000000 - Top of High Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * TempRamExit MTRR Settings:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x100000000 - Top of High Memory | Write Back</span><br><span> */</span><br><span> </span><br><span> .text</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h</span><br><span>index 0e0395a..eaf04f3 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/gpio.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/gpio.h</span><br><span>@@ -58,8 +58,8 @@</span><br><span> #define GPSSUS_COUNT 44</span><br><span> </span><br><span> /* GPIO legacy IO register settings */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_USE_MMIO 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_USE_LEGACY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_USE_MMIO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_USE_LEGACY 1</span><br><span> </span><br><span> #define GPIO_DIR_OUTPUT 0</span><br><span> #define GPIO_DIR_INPUT 1</span><br><span>@@ -317,12 +317,12 @@</span><br><span> { .pad_conf0 = GPIO_LIST_END }</span><br><span> </span><br><span> /* Common default GPIO settings */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_INPUT GPIO_INPUT_NOPU</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INPUT GPIO_INPUT_NOPU</span><br><span> #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU</span><br><span> #define GPIO_INPUT_PU GPIO_INPUT_PU_20K</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_INPUT_PD GPIO_INPUT_PD_20K</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INPUT_PD GPIO_INPUT_PD_20K</span><br><span> #define GPIO_NC GPIO_OUT_HIGH</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_DEFAULT GPIO_FUNC0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DEFAULT GPIO_FUNC0</span><br><span> </span><br><span> /* 16 DirectIRQs per supported bank */</span><br><span> #define GPIO_MAX_DIRQS 16</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>index e735f01..689d4d5 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>@@ -20,10 +20,10 @@</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(0, 100%, 40%);">-#define SINGLE_PCTL (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SINGLE_PCTL (1 << 11)</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span> #define MSR_IA32_PERF_CTL 0x199</span><br><span> #define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h</span><br><span>index ec643c1..d509b51 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/xhci.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/xhci.h</span><br><span>@@ -33,7 +33,7 @@</span><br><span> # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */</span><br><span> # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */</span><br><span> # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */</span><br><span style="color: hsl(0, 100%, 40%);">-# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */</span><br><span> # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */</span><br><span> # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */</span><br><span> # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c</span><br><span>index 61e95fa..e1e7542 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/early_spi.c</span><br><span>+++ b/src/soc/intel/baytrail/romstage/early_spi.c</span><br><span>@@ -22,7 +22,7 @@</span><br><span> #include <soc/romstage.h></span><br><span> #include <soc/spi.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CYCLE_DELAY 10 /* 10us */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CYCLE_DELAY 10 /* 10us */</span><br><span> #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */</span><br><span> </span><br><span> #define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x))</span><br><span>diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl</span><br><span>index 76804f8..ef0eaba 100644</span><br><span>--- a/src/soc/intel/broadwell/acpi/pch.asl</span><br><span>+++ b/src/soc/intel/broadwell/acpi/pch.asl</span><br><span>@@ -31,7 +31,7 @@</span><br><span> Field (RCRB, DWordAcc, Lock, Preserve)</span><br><span> {</span><br><span> Offset (0x3404), // High Performance Timer Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- HPAS, 2, // Address Select</span><br><span style="color: hsl(120, 100%, 40%);">+ HPAS, 2, // Address Select</span><br><span> , 5,</span><br><span> HPTE, 1, // Address Enable</span><br><span> }</span><br><span>diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl</span><br><span>index 6565334..44263ea 100644</span><br><span>--- a/src/soc/intel/broadwell/acpi/pci_irqs.asl</span><br><span>+++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl</span><br><span>@@ -29,11 +29,11 @@</span><br><span> Package() { 0x001cffff, 1, 0, 17 },</span><br><span> Package() { 0x001cffff, 2, 0, 18 },</span><br><span> Package() { 0x001cffff, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI 0:1d.0</span><br><span style="color: hsl(120, 100%, 40%);">+ // EHCI 0:1d.0</span><br><span> Package() { 0x001dffff, 0, 0, 19 },</span><br><span> // Audio DSP (Smart Sound) 0:13.0</span><br><span> Package() { 0x0013ffff, 0, 0, 23 },</span><br><span style="color: hsl(0, 100%, 40%);">- // XHCI 0:14.0</span><br><span style="color: hsl(120, 100%, 40%);">+ // XHCI 0:14.0</span><br><span> Package() { 0x0014ffff, 0, 0, 18 },</span><br><span> // LPC devices 0:1f.0</span><br><span> Package() { 0x001fffff, 0, 0, 22 },</span><br><span>@@ -61,11 +61,11 @@</span><br><span> Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span> Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span> Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI 0:1d.0</span><br><span style="color: hsl(120, 100%, 40%);">+ // EHCI 0:1d.0</span><br><span> Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span> // Audio DSP (Smart Sound) 0:13.0</span><br><span> Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // XHCI 0:14.0</span><br><span style="color: hsl(120, 100%, 40%);">+ // XHCI 0:14.0</span><br><span> Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span> // LPC device 0:1f.0</span><br><span> Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>index b794ede..90cd370 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>@@ -39,7 +39,7 @@</span><br><span> #define SUS_PWR_FLR (1 << 16)</span><br><span> #define PME_B0_S5_DIS (1 << 15)</span><br><span> #define PWR_FLR (1 << 14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)</span><br><span> #define DIS_SLP_X_STRCH_SUS_UP (1 << 12)</span><br><span> #define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10)</span><br><span> #define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)</span><br><span>diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c</span><br><span>index 512fbbe..d8a77b7 100644</span><br><span>--- a/src/soc/intel/cannonlake/reset.c</span><br><span>+++ b/src/soc/intel/cannonlake/reset.c</span><br><span>@@ -69,7 +69,7 @@</span><br><span> reply_size = sizeof(reply);</span><br><span> memset(&reply, 0, reply_size);</span><br><span> if (!heci_receive(&reply, &reply_size))</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span> if (reply.result != MKHI_STATUS_SUCCESS) {</span><br><span> printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n");</span><br><span> return -1;</span><br><span>diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>index 02aeefe..684f827 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>@@ -94,7 +94,7 @@</span><br><span> * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x80000008, %eax /* Address sizes leaf */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x80000008, %eax /* Address sizes leaf */</span><br><span> cpuid</span><br><span> sub $32, %al</span><br><span> movzx %al, %eax</span><br><span>@@ -193,7 +193,7 @@</span><br><span> movd %mm2, %eax</span><br><span> pushl %eax /* tsc[63:32] */</span><br><span> movd %mm1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax /* tsc[31:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax /* tsc[31:0] */</span><br><span> </span><br><span> before_carstage:</span><br><span> post_code(0x2A)</span><br><span>diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h</span><br><span>index a389e34..18d9864 100644</span><br><span>--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h</span><br><span>+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h</span><br><span>@@ -22,7 +22,7 @@</span><br><span> #define SPIBAR_BIOS_CONTROL 0xdc</span><br><span> </span><br><span> /* Bit definitions for BIOS_CONTROL */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)</span><br><span> #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1)</span><br><span> #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2)</span><br><span> #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)</span><br><span>@@ -113,21 +113,21 @@</span><br><span> #define SPIBAR_FPR_MAX 5</span><br><span> </span><br><span> /* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_0 0x01 /* Write, no address */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_1 0x03 /* Write, address required */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_2 0x03 /* READ: Read Data */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_2 0x02 /* Read, address required */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_3 0x00 /* Read, no address */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_4 0x03 /* Write, address required */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_5 0x9f /* RDID: Read ID */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_5 0x00 /* Read, no address */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPTYPE_6 0x03 /* Write, address required */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_0 0x01 /* Write, no address */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_1 0x03 /* Write, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_2 0x03 /* READ: Read Data */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_2 0x02 /* Read, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_3 0x00 /* Read, no address */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_4 0x03 /* Write, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_5 0x00 /* Read, no address */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_6 0x03 /* Write, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */</span><br><span> #define SPI_OPTYPE_7 0x02 /* Read, address required */</span><br><span> #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \</span><br><span> (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)</span><br><span>diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c</span><br><span>index 66eaddf5..811d273 100644</span><br><span>--- a/src/soc/intel/common/block/scs/sd.c</span><br><span>+++ b/src/soc/intel/common/block/scs/sd.c</span><br><span>@@ -57,7 +57,7 @@</span><br><span> static struct device_operations dev_ops = {</span><br><span> .read_resources = &pci_dev_read_resources,</span><br><span> .set_resources = &pci_dev_set_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = &pci_dev_enable_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_resources = &pci_dev_enable_resources,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .acpi_fill_ssdt_generator = &sd_fill_ssdt,</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl</span><br><span>index 262ac55..3167c18 100644</span><br><span>--- a/src/soc/intel/denverton_ns/acpi/lpc.asl</span><br><span>+++ b/src/soc/intel/denverton_ns/acpi/lpc.asl</span><br><span>@@ -177,7 +177,7 @@</span><br><span> Name(BUF0,ResourceTemplate()</span><br><span> {</span><br><span> IO(Decode16,0x02F8,0x02F8,0x01,0x08)</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}</span><br><span> })</span><br><span> Return(BUF0)</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/exit_car_fsp.S b/src/soc/intel/denverton_ns/exit_car_fsp.S</span><br><span>index 2ec625b..83d5a33 100644</span><br><span>--- a/src/soc/intel/denverton_ns/exit_car_fsp.S</span><br><span>+++ b/src/soc/intel/denverton_ns/exit_car_fsp.S</span><br><span>@@ -29,11 +29,11 @@</span><br><span> * caching settings are based on an 8MiB Flash Size given as a</span><br><span> * parameter to TempRamInit.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * TempRamExit MTRR Settings:</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x100000000 - Top of High Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * TempRamExit MTRR Settings:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x100000000 - Top of High Memory | Write Back</span><br><span> */</span><br><span> </span><br><span> .text</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h</span><br><span>index 02c226b..006102e 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h</span><br><span>@@ -56,8 +56,8 @@</span><br><span> #define GPSSUS_COUNT 44</span><br><span> </span><br><span> /* GPIO legacy IO register settings */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_USE_MMIO 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_USE_LEGACY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_USE_MMIO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_USE_LEGACY 1</span><br><span> </span><br><span> #define GPIO_DIR_OUTPUT 0</span><br><span> #define GPIO_DIR_INPUT 1</span><br><span>@@ -291,12 +291,12 @@</span><br><span> { .pad_conf0 = GPIO_LIST_END }</span><br><span> </span><br><span> /* Common default GPIO settings */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_INPUT GPIO_INPUT_NOPU</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INPUT GPIO_INPUT_NOPU</span><br><span> #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU</span><br><span> #define GPIO_INPUT_PU GPIO_INPUT_PU_20K</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_INPUT_PD GPIO_INPUT_PD_20K</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INPUT_PD GPIO_INPUT_PD_20K</span><br><span> #define GPIO_NC GPIO_INPUT_PU_20K</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_DEFAULT GPIO_FUNC0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DEFAULT GPIO_FUNC0</span><br><span> </span><br><span> /* 16 DirectIRQs per supported bank */</span><br><span> #define GPIO_MAX_DIRQS 16</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/xhci.h b/src/soc/intel/fsp_baytrail/include/soc/xhci.h</span><br><span>index ec643c1..d509b51 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/xhci.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/xhci.h</span><br><span>@@ -33,7 +33,7 @@</span><br><span> # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */</span><br><span> # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */</span><br><span> # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */</span><br><span style="color: hsl(0, 100%, 40%);">-# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */</span><br><span> # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */</span><br><span> # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */</span><br><span> # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */</span><br><span>diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c</span><br><span>index 1abe9cb..600be27 100644</span><br><span>--- a/src/soc/intel/skylake/lockdown.c</span><br><span>+++ b/src/soc/intel/skylake/lockdown.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> #include <string.h></span><br><span> </span><br><span> #define PCR_DMI_GCS 0x274C</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_GCS_BILD (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_GCS_BILD (1 << 0)</span><br><span> </span><br><span> static void lpc_lockdown_config(const struct soc_intel_skylake_config *config)</span><br><span> {</span><br><span>@@ -56,9 +56,9 @@</span><br><span> * When set, prevents GCS.BBS from being changed</span><br><span> * GCS.BBS: (Boot BIOS Strap) This field determines the destination</span><br><span> * of accesses to the BIOS memory range.</span><br><span style="color: hsl(0, 100%, 40%);">- * Bits Description</span><br><span style="color: hsl(0, 100%, 40%);">- * "0b": SPI</span><br><span style="color: hsl(0, 100%, 40%);">- * "1b": LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bits Description</span><br><span style="color: hsl(120, 100%, 40%);">+ * "0b": SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * "1b": LPC/eSPI</span><br><span> */</span><br><span> pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);</span><br><span> }</span><br><span>diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h</span><br><span>index bfeebae..9af4b20 100644</span><br><span>--- a/src/soc/nvidia/tegra/types.h</span><br><span>+++ b/src/soc/nvidia/tegra/types.h</span><br><span>@@ -18,7 +18,7 @@</span><br><span> </span><br><span> #define EFAULT 1</span><br><span> #define EINVAL 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define ETIMEDOUT 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define ETIMEDOUT 3</span><br><span> #define ENOSPC 4</span><br><span> #define ENOSYS 5</span><br><span> #define EPTR 6</span><br><span>diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c</span><br><span>index dce6ad2..7002906 100644</span><br><span>--- a/src/soc/nvidia/tegra124/display.c</span><br><span>+++ b/src/soc/nvidia/tegra124/display.c</span><br><span>@@ -216,7 +216,7 @@</span><br><span> {</span><br><span> struct soc_nvidia_tegra124_config *config = dev->chip_info;</span><br><span> struct display_controller *disp_ctrl = (void *)config->display_controller;</span><br><span style="color: hsl(0, 100%, 40%);">- struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;</span><br><span> struct tegra_dc *dc = &dc_data;</span><br><span> u32 plld_rate;</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h</span><br><span>index 165b823..d28e71e 100644</span><br><span>--- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h</span><br><span>+++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h</span><br><span>@@ -469,12 +469,12 @@</span><br><span> #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT)</span><br><span> </span><br><span> /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCLK_DISABLE (1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCLK_DIVISOR_SHIFT 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCLK_DISABLE (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCLK_DIVISOR_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCLK_DISABLE (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCLK_DIVISOR_SHIFT 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCLK_DISABLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCLK_DIVISOR_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span> </span><br><span> /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */</span><br><span> #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)</span><br><span>diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c</span><br><span>index 3de63f9..400e9b5 100644</span><br><span>--- a/src/soc/nvidia/tegra124/sor.c</span><br><span>+++ b/src/soc/nvidia/tegra124/sor.c</span><br><span>@@ -604,8 +604,8 @@</span><br><span> static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,</span><br><span> int is_lvds)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- const struct tegra_dc *dc = sor->dc;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct tegra_dc_dp_data *dp = dc->out;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct tegra_dc *dc = sor->dc;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct tegra_dc_dp_data *dp = dc->out;</span><br><span> const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg;</span><br><span> const struct soc_nvidia_tegra124_config *config = dc->config;</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h</span><br><span>index 65fb8fe..9f19402 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h</span><br><span>@@ -414,7 +414,7 @@</span><br><span> #define PLLM_MISC2_KCP_SHIFT 1</span><br><span> #define PLLM_MISC2_KVCO_SHIFT 0</span><br><span> #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLLM_EN_LCKDET (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLLM_EN_LCKDET (1 << 4)</span><br><span> </span><br><span> /* PLLU specific registers */</span><br><span> #define PLLU_MISC_IDDQ (1U << 31)</span><br><span>@@ -525,12 +525,12 @@</span><br><span> #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT)</span><br><span> </span><br><span> /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCLK_DISABLE (1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCLK_DIVISOR_SHIFT 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCLK_DISABLE (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCLK_DIVISOR_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCLK_DISABLE (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCLK_DIVISOR_SHIFT 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCLK_DISABLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCLK_DIVISOR_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)</span><br><span> </span><br><span> /* CPU_SOFTRST_CTRL2_0 0x388 */</span><br><span> #define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff</span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h</span><br><span>index 4b4f14e..dbaaa22 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h</span><br><span>@@ -149,7 +149,7 @@</span><br><span> #define PKT_LP (1 << 30)</span><br><span> #define NUM_PKT_SEQ 12</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20)</span><br><span> #define DSIB_MODE_SHIFT 1</span><br><span> #define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT)</span><br><span> #define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT)</span><br><span>diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h</span><br><span>index 4a3aa49..42838bb 100644</span><br><span>--- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h</span><br><span>+++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h</span><br><span>@@ -101,12 +101,12 @@</span><br><span> #define USB_HOST1_PHY_BASE 0x110F8800</span><br><span> </span><br><span> #define GSBI_4 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define UART1_DM_BASE 0x12450000</span><br><span style="color: hsl(0, 100%, 40%);">-#define UART_GSBI1_BASE 0x12440000</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART1_DM_BASE 0x12450000</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_GSBI1_BASE 0x12440000</span><br><span> #define UART2_DM_BASE 0x12490000</span><br><span> #define UART_GSBI2_BASE 0x12480000</span><br><span style="color: hsl(0, 100%, 40%);">-#define UART4_DM_BASE 0x16340000</span><br><span style="color: hsl(0, 100%, 40%);">-#define UART_GSBI4_BASE 0x16300000</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART4_DM_BASE 0x16340000</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_GSBI4_BASE 0x16300000</span><br><span> </span><br><span> #define UART2_DM_BASE 0x12490000</span><br><span> #define UART_GSBI2_BASE 0x12480000</span><br><span>diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c</span><br><span>index a8d9910..f8f4e4d 100644</span><br><span>--- a/src/soc/qualcomm/ipq806x/usb.c</span><br><span>+++ b/src/soc/qualcomm/ipq806x/usb.c</span><br><span>@@ -123,7 +123,7 @@</span><br><span> write32(&dwc3->uctl,</span><br><span> 0x32 << 22 | /* (default) reference clock period in ns */</span><br><span> 0x1 << 15 | /* (default) XHCI compliant device addressing */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x10 << 0); /* (default) devices time out after 32us */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10 << 0); /* (default) devices time out after 32us */</span><br><span> </span><br><span> udelay(5);</span><br><span> </span><br><span>@@ -149,7 +149,7 @@</span><br><span> 0x1 << 18 | /* use ref clock from core */</span><br><span> 0x1 << 17 | /* (default) unclamp DPSE VLS */</span><br><span> 0x1 << 11 | /* force xo/bias/pll to stay on in suspend */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1 << 9 | /* (default) unclamp IDHV */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 9 | /* (default) unclamp IDHV */</span><br><span> 0x1 << 8 | /* (default) unclamp VLS (again???) */</span><br><span> 0x1 << 7 | /* (default) unclamp HV VLS */</span><br><span> 0x7 << 4 | /* select frequency (no idea which one) */</span><br><span>diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h</span><br><span>index 457c51d..f304d8f 100644</span><br><span>--- a/src/soc/rockchip/rk3399/include/soc/mipi.h</span><br><span>+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h</span><br><span>@@ -233,7 +233,7 @@</span><br><span> #define THS_PRE_PROGRAM_EN BIT(7)</span><br><span> #define THS_ZERO_PROGRAM_EN BIT(6)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10</span><br><span> #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11</span><br><span> #define PLL_LPF_AND_CP_CONTROL 0x12</span><br><span> #define PLL_INPUT_DIVIDER_RATIO 0x17</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26651">change 26651</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26651"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 </div>
<div style="display:none"> Gerrit-Change-Number: 26651 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>