<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26645">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block/cpu: Perform AP init if publish_mp_service_ppi=1<br><br>This patch ensures that coreboot can still perform AP initialziation<br>if publish_mp_service_ppi is enabled through mainboard devicetree.cb<br><br>Change-Id: I699c5457898c1dea0b6f78ec74dd02fb400db14f<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/apollolake/chip.h<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/common/block/cpu/mp_init.c<br>M src/soc/intel/skylake/chip.h<br>4 files changed, 22 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/26645/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h</span><br><span>index f00924f..5103b54 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.h</span><br><span>+++ b/src/soc/intel/apollolake/chip.h</span><br><span>@@ -158,6 +158,13 @@</span><br><span> * 0: Initialize(Default), 1: Skip</span><br><span> */</span><br><span> uint8_t FspSkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Create MP service PPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Don't create PPI structure</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Create PPI structure</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t publish_mp_service_ppi;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_apollolake_config config_t;</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 8fdb964..595e873 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -285,6 +285,13 @@</span><br><span> /* Intel VT configuration */</span><br><span> uint8_t VtdDisable;</span><br><span> uint8_t VmxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Create MP service PPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Don't create PPI structure</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Create PPI structure</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t publish_mp_service_ppi;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_cannonlake_config config_t;</span><br><span>diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>index 7a3ba87..6a96065 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>@@ -126,7 +126,7 @@</span><br><span> assert(dev != NULL);</span><br><span> config_t *config = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (config->FspSkipMpInit)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->FspSkipMpInit || config->publish_mp_service_ppi)</span><br><span> return true;</span><br><span> </span><br><span> return false;</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 2523554..f8c876e 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -563,6 +563,13 @@</span><br><span> </span><br><span> /* Enable/Disable Sata power optimization */</span><br><span> u8 SataPwrOptEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Create MP service PPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Don't create PPI structure</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Create PPI structure</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 publish_mp_service_ppi;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_skylake_config config_t;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26645">change 26645</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I699c5457898c1dea0b6f78ec74dd02fb400db14f </div>
<div style="display:none"> Gerrit-Change-Number: 26645 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>