<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26620">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/gigabyte: Get rid of whitespace before tab<br><br>Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb<br>M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb<br>M src/mainboard/gigabyte/m57sli/romstage.c<br>M src/mainboard/gigabyte/ma785gm/devicetree.cb<br>M src/mainboard/gigabyte/ma785gm/dsdt.asl<br>M src/mainboard/gigabyte/ma785gmt/devicetree.cb<br>M src/mainboard/gigabyte/ma785gmt/dsdt.asl<br>M src/mainboard/gigabyte/ma785gmt/mainboard.c<br>M src/mainboard/gigabyte/ma78gm/devicetree.cb<br>M src/mainboard/gigabyte/ma78gm/dsdt.asl<br>10 files changed, 67 insertions(+), 67 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/26620/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb</span><br><span>index 39f7908..d948398 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb</span><br><span>+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb</span><br><span>@@ -28,7 +28,7 @@</span><br><span> device pci 0.0 on # Host Bridge</span><br><span> subsystemid 0x1458 0x5000</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.0 on # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on # Integrated graphics controller</span><br><span> subsystemid 0x1458 0xd000</span><br><span> end</span><br><span> device pci 2.1 on # Integrated graphics controller 2</span><br><span>diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb</span><br><span>index 3ba8558..9102b82 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb</span><br><span>+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb</span><br><span>@@ -81,7 +81,7 @@</span><br><span> irq 0x70 = 7</span><br><span> drq 0x74 = 4</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.4 on # Environment Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.4 on # Environment Controller</span><br><span> io 0x60 = 0x0a30</span><br><span> irq 0x70 = 9</span><br><span> io 0x62 = 0x0a20</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c</span><br><span>index 3261c5d..8dc263c 100644</span><br><span>--- a/src/mainboard/gigabyte/m57sli/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/romstage.c</span><br><span>@@ -136,7 +136,7 @@</span><br><span> pnp_write_config(GPIO_DEV, 0x64, 0x08);</span><br><span> pnp_write_config(GPIO_DEV, 0x65, 0x20);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> pnp_exit_ext_func_mode(SERIAL_DEV);</span><br><span> #endif</span><br><span> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb</span><br><span>index c7d9932..65c76fb 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gm/devicetree.cb</span><br><span>+++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9601</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9601</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 off end # PCIE P2P bridge 0x960b</span><br><span>@@ -41,7 +41,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl</span><br><span>index 700e4ae..bc04279 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gm/dsdt.asl</span><br><span>+++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1520,7 +1520,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1634,7 +1634,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb</span><br><span>index bd98313..a38ebd8 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb</span><br><span>+++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 on end # PCIE P2P bridge 0x960b</span><br><span>@@ -41,7 +41,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl</span><br><span>index 700e4ae..bc04279 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl</span><br><span>+++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1520,7 +1520,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1634,7 +1634,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c</span><br><span>index acc88fd..0bb626b 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c</span><br><span>+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c</span><br><span>@@ -165,7 +165,7 @@</span><br><span> dword = pci_read_config32(sm_dev, 0xfc);</span><br><span> dword &= ~(1 << 10);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* When the gpio40 is configured as GPIO, this will represent the output value*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* When the gpio40 is configured as GPIO, this will represent the output value*/</span><br><span> /* 1 :enable two x8 , 0 : master slot enable only */</span><br><span> dword &= ~(1 << 26);</span><br><span> pci_write_config32(sm_dev, 0xfc, dword);</span><br><span>diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb</span><br><span>index 8d81fbe..3e69cb3 100644</span><br><span>--- a/src/mainboard/gigabyte/ma78gm/devicetree.cb</span><br><span>+++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 off end # PCIE P2P bridge 0x960b</span><br><span>@@ -40,7 +40,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl</span><br><span>index 700e4ae..bc04279 100644</span><br><span>--- a/src/mainboard/gigabyte/ma78gm/dsdt.asl</span><br><span>+++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1520,7 +1520,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1634,7 +1634,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26620">change 26620</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26620"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86 </div>
<div style="display:none"> Gerrit-Change-Number: 26620 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>