<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26607">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/amg: Get rid of whitespace before tab<br><br>Change-Id: I3acc5b0c3895459a7aba53a422a978e31f652aa9<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/amd/bettong/acpi/gpe.asl<br>M src/mainboard/amd/bettong/dsdt.asl<br>M src/mainboard/amd/bimini_fam10/devicetree.cb<br>M src/mainboard/amd/bimini_fam10/dsdt.asl<br>M src/mainboard/amd/bimini_fam10/romstage.c<br>M src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl<br>M src/mainboard/amd/db-ft3b-lc/dsdt.asl<br>M src/mainboard/amd/dbm690t/devicetree.cb<br>M src/mainboard/amd/dbm690t/dsdt.asl<br>M src/mainboard/amd/gardenia/acpi/gpe.asl<br>M src/mainboard/amd/inagua/acpi/gpe.asl<br>M src/mainboard/amd/inagua/acpi/sleep.asl<br>M src/mainboard/amd/inagua/acpi/usb_oc.asl<br>M src/mainboard/amd/inagua/buildOpts.c<br>M src/mainboard/amd/inagua/mainboard.c<br>M src/mainboard/amd/lamar/acpi/gpe.asl<br>M src/mainboard/amd/lamar/acpi/sleep.asl<br>M src/mainboard/amd/mahogany/devicetree.cb<br>M src/mainboard/amd/mahogany/dsdt.asl<br>M src/mainboard/amd/mahogany_fam10/devicetree.cb<br>M src/mainboard/amd/mahogany_fam10/dsdt.asl<br>M src/mainboard/amd/olivehill/acpi/gpe.asl<br>M src/mainboard/amd/olivehill/dsdt.asl<br>M src/mainboard/amd/olivehillplus/acpi/gpe.asl<br>M src/mainboard/amd/olivehillplus/dsdt.asl<br>M src/mainboard/amd/parmer/acpi/gpe.asl<br>M src/mainboard/amd/parmer/acpi/sleep.asl<br>M src/mainboard/amd/parmer/buildOpts.c<br>M src/mainboard/amd/persimmon/acpi/gpe.asl<br>M src/mainboard/amd/persimmon/acpi/sleep.asl<br>M src/mainboard/amd/pistachio/devicetree.cb<br>M src/mainboard/amd/pistachio/dsdt.asl<br>M src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl<br>M src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl<br>M src/mainboard/amd/serengeti_cheetah/devicetree.cb<br>M src/mainboard/amd/south_station/acpi/gpe.asl<br>M src/mainboard/amd/south_station/acpi/sleep.asl<br>M src/mainboard/amd/south_station/acpi/usb_oc.asl<br>M src/mainboard/amd/south_station/devicetree.cb<br>M src/mainboard/amd/south_station/mainboard.c<br>M src/mainboard/amd/thatcher/acpi/gpe.asl<br>M src/mainboard/amd/thatcher/acpi/sleep.asl<br>M src/mainboard/amd/thatcher/buildOpts.c<br>M src/mainboard/amd/tilapia_fam10/devicetree.cb<br>M src/mainboard/amd/tilapia_fam10/dsdt.asl<br>M src/mainboard/amd/tilapia_fam10/mainboard.c<br>M src/mainboard/amd/torpedo/devicetree.cb<br>M src/mainboard/amd/torpedo/dsdt.asl<br>M src/mainboard/amd/torpedo/gpio.c<br>M src/mainboard/amd/union_station/acpi/gpe.asl<br>M src/mainboard/amd/union_station/acpi/sleep.asl<br>M src/mainboard/amd/union_station/acpi/usb_oc.asl<br>M src/mainboard/amd/union_station/devicetree.cb<br>M src/mainboard/amd/union_station/mainboard.c<br>54 files changed, 213 insertions(+), 213 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26607/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl</span><br><span>index 9a84698..87b0d21 100644</span><br><span>--- a/src/mainboard/amd/bettong/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/bettong/acpi/gpe.asl</span><br><span>@@ -71,4 +71,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl</span><br><span>index 37257c4..505b519 100644</span><br><span>--- a/src/mainboard/amd/bettong/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/bettong/dsdt.asl</span><br><span>@@ -45,7 +45,7 @@</span><br><span> </span><br><span> /* System Bus */</span><br><span> Scope(\_SB) { /* Start \_SB scope */</span><br><span style="color: hsl(0, 100%, 40%);">- /* global utility methods expected within the \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global utility methods expected within the \_SB scope */</span><br><span> #include <arch/x86/acpi/globutil.asl></span><br><span> </span><br><span> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */</span><br><span>diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb</span><br><span>index 0bcc9c1..ba6a0fa 100644</span><br><span>--- a/src/mainboard/amd/bimini_fam10/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/bimini_fam10/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 off end # PCIE P2P bridge 0x960b</span><br><span>@@ -38,7 +38,7 @@</span><br><span> device pci 12.2 on end # USB</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl</span><br><span>index c6b0ad2..dae9333 100644</span><br><span>--- a/src/mainboard/amd/bimini_fam10/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/bimini_fam10/dsdt.asl</span><br><span>@@ -234,9 +234,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -832,7 +832,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -847,13 +847,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1020,7 +1020,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1043,19 +1043,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1067,7 +1067,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1084,7 +1084,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1115,7 +1115,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1125,7 +1125,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1477,7 +1477,7 @@</span><br><span> )</span><br><span> #if 0</span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1607,7 +1607,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c</span><br><span>index 0c26416..d4397b2 100644</span><br><span>--- a/src/mainboard/amd/bimini_fam10/romstage.c</span><br><span>+++ b/src/mainboard/amd/bimini_fam10/romstage.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> </span><br><span> /* enable port80 decoding and southbridge poweron init */</span><br><span> sb800_lpc_port80();</span><br><span style="color: hsl(0, 100%, 40%);">- inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */</span><br><span style="color: hsl(120, 100%, 40%);">+ inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */</span><br><span> }</span><br><span> </span><br><span> post_code(0x30);</span><br><span>diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl</span><br><span>index 9a84698..87b0d21 100644</span><br><span>--- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl</span><br><span>@@ -71,4 +71,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/db-ft3b-lc/dsdt.asl b/src/mainboard/amd/db-ft3b-lc/dsdt.asl</span><br><span>index 03d46dc..549adc0 100644</span><br><span>--- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/db-ft3b-lc/dsdt.asl</span><br><span>@@ -46,7 +46,7 @@</span><br><span> </span><br><span> /* System Bus */</span><br><span> Scope(\_SB) { /* Start \_SB scope */</span><br><span style="color: hsl(0, 100%, 40%);">- /* global utility methods expected within the \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global utility methods expected within the \_SB scope */</span><br><span> #include <arch/x86/acpi/globutil.asl></span><br><span> </span><br><span> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */</span><br><span>diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb</span><br><span>index 898537b..c7c6412 100644</span><br><span>--- a/src/mainboard/amd/dbm690t/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/dbm690t/devicetree.cb</span><br><span>@@ -19,7 +19,7 @@</span><br><span> chip northbridge/amd/amdk8</span><br><span> device pci 18.0 on # southbridge</span><br><span> chip southbridge/amd/rs690</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x7910</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x7910</span><br><span> device pci 1.0 on # Internal Graphics P2P bridge 0x7912</span><br><span> device pci 5.0 on end # Internal Graphics 0x791F</span><br><span> end</span><br><span>@@ -48,7 +48,7 @@</span><br><span> device pci 13.3 on end # USB 0x438a</span><br><span> device pci 13.4 on end # USB 0x438b</span><br><span> device pci 13.5 on end # USB 2 0x4386</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM 0x4385</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM 0x4385</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl</span><br><span>index 748c9fb..a3a7726 100644</span><br><span>--- a/src/mainboard/amd/dbm690t/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/dbm690t/dsdt.asl</span><br><span>@@ -198,9 +198,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -799,7 +799,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -815,13 +815,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -988,7 +988,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1011,19 +1011,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1035,7 +1035,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1052,7 +1052,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1083,7 +1083,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1093,7 +1093,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1462,7 +1462,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1576,7 +1576,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl</span><br><span>index e713ad6..6429bc6 100644</span><br><span>--- a/src/mainboard/amd/gardenia/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/gardenia/acpi/gpe.asl</span><br><span>@@ -66,4 +66,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl</span><br><span>index 2f22758..30e6fdc 100644</span><br><span>--- a/src/mainboard/amd/inagua/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/inagua/acpi/gpe.asl</span><br><span>@@ -72,7 +72,7 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span> </span><br><span> /* Contains the GPEs for USB overcurrent */</span><br><span> #include "usb_oc.asl"</span><br><span>diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl</span><br><span>index d7cf365..ec38a8a 100644</span><br><span>--- a/src/mainboard/amd/inagua/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/inagua/acpi/sleep.asl</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl</span><br><span>index 299d4aa..6e9c701 100644</span><br><span>--- a/src/mainboard/amd/inagua/acpi/usb_oc.asl</span><br><span>+++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl</span><br><span>@@ -36,7 +36,7 @@</span><br><span> </span><br><span> Method(UCOC, 0) {</span><br><span> Sleep(20)</span><br><span style="color: hsl(0, 100%, 40%);">- Store(0x13,CMTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x13,CMTI)</span><br><span> Store(0,GPSL)</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c</span><br><span>index ff947a0..c18bfd2 100644</span><br><span>--- a/src/mainboard/amd/inagua/buildOpts.c</span><br><span>+++ b/src/mainboard/amd/inagua/buildOpts.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> </span><br><span> /* Select the CPU socket type. */</span><br><span> #define INSTALL_G34_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#define INSTALL_C32_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_C32_SOCKET_SUPPORT FALSE</span><br><span> #define INSTALL_S1G3_SOCKET_SUPPORT FALSE</span><br><span> #define INSTALL_S1G4_SOCKET_SUPPORT FALSE</span><br><span> #define INSTALL_ASB2_SOCKET_SUPPORT FALSE</span><br><span>@@ -53,7 +53,7 @@</span><br><span> */</span><br><span> </span><br><span> #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE</span><br><span> #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE</span><br><span> #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c</span><br><span>index afe6c87..27870f4 100644</span><br><span>--- a/src/mainboard/amd/inagua/mainboard.c</span><br><span>+++ b/src/mainboard/amd/inagua/mainboard.c</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> </span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span> </span><br><span> static void init_gpios(void)</span><br><span> {</span><br><span>diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl</span><br><span>index c5753ee..297d9b4 100644</span><br><span>--- a/src/mainboard/amd/lamar/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/lamar/acpi/gpe.asl</span><br><span>@@ -70,4 +70,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl</span><br><span>index 2d26a54..f7edfb9 100644</span><br><span>--- a/src/mainboard/amd/lamar/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/lamar/acpi/sleep.asl</span><br><span>@@ -44,7 +44,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb</span><br><span>index 56efd84..321f760 100644</span><br><span>--- a/src/mainboard/amd/mahogany/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/mahogany/devicetree.cb</span><br><span>@@ -19,7 +19,7 @@</span><br><span> chip northbridge/amd/amdk8</span><br><span> device pci 18.0 on # southbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 on end # PCIE P2P bridge 0x960b</span><br><span>@@ -49,7 +49,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl</span><br><span>index dfffa87..983f025 100644</span><br><span>--- a/src/mainboard/amd/mahogany/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/mahogany/dsdt.asl</span><br><span>@@ -197,9 +197,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -795,7 +795,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -811,13 +811,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -984,7 +984,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1007,19 +1007,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1031,7 +1031,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1048,7 +1048,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1079,7 +1079,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1089,7 +1089,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1478,7 +1478,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1592,7 +1592,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb</span><br><span>index 5000b0c..dba1470 100644</span><br><span>--- a/src/mainboard/amd/mahogany_fam10/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 on end # PCIE P2P bridge 0x960b</span><br><span>@@ -40,7 +40,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl</span><br><span>index 6c72744..3c47bd6 100644</span><br><span>--- a/src/mainboard/amd/mahogany_fam10/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1520,7 +1520,7 @@</span><br><span> 0xF300 /* length */</span><br><span> )</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> #if 0</span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span>@@ -1652,7 +1652,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl</span><br><span>index 9a84698..87b0d21 100644</span><br><span>--- a/src/mainboard/amd/olivehill/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/olivehill/acpi/gpe.asl</span><br><span>@@ -71,4 +71,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl</span><br><span>index e709989..e2d0208 100644</span><br><span>--- a/src/mainboard/amd/olivehill/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/olivehill/dsdt.asl</span><br><span>@@ -46,7 +46,7 @@</span><br><span> </span><br><span> /* System Bus */</span><br><span> Scope(\_SB) { /* Start \_SB scope */</span><br><span style="color: hsl(0, 100%, 40%);">- /* global utility methods expected within the \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global utility methods expected within the \_SB scope */</span><br><span> #include <arch/x86/acpi/globutil.asl></span><br><span> </span><br><span> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */</span><br><span>diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl</span><br><span>index 9a84698..87b0d21 100644</span><br><span>--- a/src/mainboard/amd/olivehillplus/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/olivehillplus/acpi/gpe.asl</span><br><span>@@ -71,4 +71,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl</span><br><span>index 03d46dc..549adc0 100644</span><br><span>--- a/src/mainboard/amd/olivehillplus/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/olivehillplus/dsdt.asl</span><br><span>@@ -46,7 +46,7 @@</span><br><span> </span><br><span> /* System Bus */</span><br><span> Scope(\_SB) { /* Start \_SB scope */</span><br><span style="color: hsl(0, 100%, 40%);">- /* global utility methods expected within the \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global utility methods expected within the \_SB scope */</span><br><span> #include <arch/x86/acpi/globutil.asl></span><br><span> </span><br><span> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */</span><br><span>diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl</span><br><span>index 8e7840f..32d5a2a 100644</span><br><span>--- a/src/mainboard/amd/parmer/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/parmer/acpi/gpe.asl</span><br><span>@@ -72,4 +72,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl</span><br><span>index 947a2f2..d516cce 100644</span><br><span>--- a/src/mainboard/amd/parmer/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/parmer/acpi/sleep.asl</span><br><span>@@ -44,7 +44,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c</span><br><span>index af2046d..4380b06 100644</span><br><span>--- a/src/mainboard/amd/parmer/buildOpts.c</span><br><span>+++ b/src/mainboard/amd/parmer/buildOpts.c</span><br><span>@@ -155,8 +155,8 @@</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED</span><br><span> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED</span><br><span style="color: hsl(0, 100%, 40%);">-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span> #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl</span><br><span>index 2f22758..30e6fdc 100644</span><br><span>--- a/src/mainboard/amd/persimmon/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/persimmon/acpi/gpe.asl</span><br><span>@@ -72,7 +72,7 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span> </span><br><span> /* Contains the GPEs for USB overcurrent */</span><br><span> #include "usb_oc.asl"</span><br><span>diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl</span><br><span>index d7cf365..ec38a8a 100644</span><br><span>--- a/src/mainboard/amd/persimmon/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/persimmon/acpi/sleep.asl</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb</span><br><span>index 805df7c..c5459b0 100644</span><br><span>--- a/src/mainboard/amd/pistachio/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/pistachio/devicetree.cb</span><br><span>@@ -19,7 +19,7 @@</span><br><span> chip northbridge/amd/amdk8</span><br><span> device pci 18.0 on # southbridge, K8 HT Configuration</span><br><span> chip southbridge/amd/rs690</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x7910</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x7910</span><br><span> # device pci 0.1 off end # CLK</span><br><span> device pci 1.0 on # Internal Graphics P2P bridge 0x7912</span><br><span> device pci 5.0 on end # Internal Graphics 0x791F</span><br><span>@@ -49,7 +49,7 @@</span><br><span> device pci 13.3 on end # USB 0x438a</span><br><span> device pci 13.4 on end # USB 0x438b</span><br><span> device pci 13.5 on end # USB 2 0x4386</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM 0x4385</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM 0x4385</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl</span><br><span>index 79589a8..f4500f5 100644</span><br><span>--- a/src/mainboard/amd/pistachio/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/pistachio/dsdt.asl</span><br><span>@@ -198,9 +198,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -799,7 +799,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -814,13 +814,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -987,7 +987,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1010,19 +1010,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1034,7 +1034,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1051,7 +1051,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1082,7 +1082,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1092,7 +1092,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1385,7 +1385,7 @@</span><br><span> )</span><br><span> </span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1499,7 +1499,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl</span><br><span>index b0dbb45..0de9296 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl</span><br><span>@@ -51,14 +51,14 @@</span><br><span> If (LEqual (^DNCG, Ones)) {</span><br><span> Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8</span><br><span> Store (0x00, Local1)</span><br><span style="color: hsl(0, 100%, 40%);">- While (LLess (Local1, 0x04))</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- // Update the GSI according to HCIN</span><br><span style="color: hsl(120, 100%, 40%);">+ While (LLess (Local1, 0x04))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ // Update the GSI according to HCIN</span><br><span> Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)</span><br><span> Add(Local2, Local0, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))</span><br><span> Increment (Local1)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> Store (0x00, ^DNCG)</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl</span><br><span>index 02b9ee2..898fb1c 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl</span><br><span>@@ -51,14 +51,14 @@</span><br><span> If (LEqual (^DNCG, Ones)) {</span><br><span> Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14</span><br><span> Store (0x00, Local1)</span><br><span style="color: hsl(0, 100%, 40%);">- While (LLess (Local1, 0x04))</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- // Update the GSI according to HCIN</span><br><span style="color: hsl(120, 100%, 40%);">+ While (LLess (Local1, 0x04))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ // Update the GSI according to HCIN</span><br><span> Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)</span><br><span> Add(Local2, Local0, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))</span><br><span> Increment (Local1)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> Store (0x00, ^DNCG)</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb</span><br><span>index 8ff0e3e..f8141e0 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb</span><br><span>@@ -28,43 +28,43 @@</span><br><span> device pci 1.0 on</span><br><span> chip superio/winbond/w83627hf</span><br><span> device pnp 2e.0 off # Floppy</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f0</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 6</span><br><span style="color: hsl(0, 100%, 40%);">- drq 0x74 = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 2</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.1 off # Parallel Port</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x378</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 off # Parallel Port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.2 on # Com1</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # Com1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.3 off # Com2</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x2f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off # Com2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.5 on # Keyboard</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x60</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x62 = 0x64</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span> irq 0x72 = 12</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.6 off # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off # CIR</span><br><span> io 0x60 = 0x100</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.7 off # GAME_MIDI_GIPO1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off # GAME_MIDI_GIPO1</span><br><span> io 0x60 = 0x220</span><br><span> io 0x62 = 0x300</span><br><span> irq 0x70 = 9</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.8 off end # GPIO2</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.9 off end # GPIO3</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.a off end # ACPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span> irq 0x70 = 5</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span> end</span><br><span> end</span><br><span> device pci 1.1 on end</span><br><span>@@ -115,8 +115,8 @@</span><br><span> end # acpi</span><br><span> device pci 1.5 off end</span><br><span> device pci 1.6 off end</span><br><span style="color: hsl(0, 100%, 40%);">- register "ide0_enable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ide1_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide0_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide1_enable" = "1"</span><br><span> end</span><br><span> end # device pci 18.0</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl</span><br><span>index 2f22758..30e6fdc 100644</span><br><span>--- a/src/mainboard/amd/south_station/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/south_station/acpi/gpe.asl</span><br><span>@@ -72,7 +72,7 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span> </span><br><span> /* Contains the GPEs for USB overcurrent */</span><br><span> #include "usb_oc.asl"</span><br><span>diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl</span><br><span>index d7cf365..ec38a8a 100644</span><br><span>--- a/src/mainboard/amd/south_station/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/south_station/acpi/sleep.asl</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl</span><br><span>index 299d4aa..6e9c701 100644</span><br><span>--- a/src/mainboard/amd/south_station/acpi/usb_oc.asl</span><br><span>+++ b/src/mainboard/amd/south_station/acpi/usb_oc.asl</span><br><span>@@ -36,7 +36,7 @@</span><br><span> </span><br><span> Method(UCOC, 0) {</span><br><span> Sleep(20)</span><br><span style="color: hsl(0, 100%, 40%);">- Store(0x13,CMTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x13,CMTI)</span><br><span> Store(0,GPSL)</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb</span><br><span>index 0488f5b..86378ee 100644</span><br><span>--- a/src/mainboard/amd/south_station/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/south_station/devicetree.cb</span><br><span>@@ -78,7 +78,7 @@</span><br><span> end # f81865f</span><br><span> end #LPC</span><br><span> device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.5 on end # USB 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # USB 2</span><br><span> device pci 15.0 off end # PCIe PortA</span><br><span> device pci 15.1 off end # PCIe PortB</span><br><span> device pci 15.2 off end # PCIe PortC</span><br><span>@@ -86,7 +86,7 @@</span><br><span> device pci 16.0 off end # OHCI USB3</span><br><span> device pci 16.2 off end # EHCI USB3</span><br><span> register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)</span><br><span style="color: hsl(0, 100%, 40%);">- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE</span><br><span> end #southbridge/amd/cimx/sb800</span><br><span> # end # device pci 18.0</span><br><span> # These seem unnecessary</span><br><span>diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c</span><br><span>index d069838..0edb606 100644</span><br><span>--- a/src/mainboard/amd/south_station/mainboard.c</span><br><span>+++ b/src/mainboard/amd/south_station/mainboard.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <device/device.h></span><br><span> </span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span> </span><br><span> /**</span><br><span> * Southstation using SB GPIO 17/18 to control the Red/Green LED</span><br><span>diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl</span><br><span>index 8e7840f..32d5a2a 100644</span><br><span>--- a/src/mainboard/amd/thatcher/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/thatcher/acpi/gpe.asl</span><br><span>@@ -72,4 +72,4 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl</span><br><span>index 1dc590f..9dd24e4 100644</span><br><span>--- a/src/mainboard/amd/thatcher/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/thatcher/acpi/sleep.asl</span><br><span>@@ -44,7 +44,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c</span><br><span>index 4b7bb69..54acc80 100644</span><br><span>--- a/src/mainboard/amd/thatcher/buildOpts.c</span><br><span>+++ b/src/mainboard/amd/thatcher/buildOpts.c</span><br><span>@@ -155,8 +155,8 @@</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED</span><br><span> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED</span><br><span style="color: hsl(0, 100%, 40%);">-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span> #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb</span><br><span>index 77fd875..06e33f7 100644</span><br><span>--- a/src/mainboard/amd/tilapia_fam10/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb</span><br><span>@@ -10,7 +10,7 @@</span><br><span> chip northbridge/amd/amdfam10</span><br><span> device pci 18.0 on # northbridge</span><br><span> chip southbridge/amd/rs780</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # HT 0x9600</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT 0x9600</span><br><span> device pci 1.0 on end # Internal Graphics P2P bridge 0x9602</span><br><span> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603</span><br><span> device pci 3.0 on end # PCIE P2P bridge 0x960b</span><br><span>@@ -41,7 +41,7 @@</span><br><span> device pci 13.0 on end # USB</span><br><span> device pci 13.1 on end # USB</span><br><span> device pci 13.2 on end # USB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span> chip drivers/generic/generic #dimm 0-0-0</span><br><span> device i2c 50 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl</span><br><span>index 4afab9c..218f826 100644</span><br><span>--- a/src/mainboard/amd/tilapia_fam10/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl</span><br><span>@@ -239,9 +239,9 @@</span><br><span> PWMK, 1,</span><br><span> PWNS, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ,7, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R617,1, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Offset(0x61), */ /* Options_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ,7, */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* R617,1, */</span><br><span> </span><br><span> Offset(0x65), /* UsbPMControl */</span><br><span> , 4,</span><br><span>@@ -837,7 +837,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -853,13 +853,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -1026,7 +1026,7 @@</span><br><span> </span><br><span> /* PCIe HotPlug event */</span><br><span> /* Method(_L0F) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L0F\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L0F\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1049,19 +1049,19 @@</span><br><span> </span><br><span> /* GPM0 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L13) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L13\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L13\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM1 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L14) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L14\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L14\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span> /* GPM2 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L15) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L15\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L15\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1073,7 +1073,7 @@</span><br><span> </span><br><span> /* GPM8 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L17) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L17\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L17\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1090,7 +1090,7 @@</span><br><span> </span><br><span> /* GPM4 SCI event - Moved to USB.asl */</span><br><span> /* Method(_L19) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L19\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L19\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1121,7 +1121,7 @@</span><br><span> </span><br><span> /* GPIO2 or GPIO66 SCI event */</span><br><span> /* Method(_L1E) {</span><br><span style="color: hsl(0, 100%, 40%);">- * DBGO("\\_GPE\\_L1E\n")</span><br><span style="color: hsl(120, 100%, 40%);">+ * DBGO("\\_GPE\\_L1E\n")</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span>@@ -1131,7 +1131,7 @@</span><br><span> * }</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> #include "acpi/usb.asl"</span><br><span> </span><br><span>@@ -1521,7 +1521,7 @@</span><br><span> </span><br><span> #if 0</span><br><span> Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */</span><br><span> Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */</span><br><span> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */</span><br><span> </span><br><span>@@ -1655,7 +1655,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\PWDE)</span><br><span> * }</span><br><span> */</span><br><span> } /* End Method(_SB._INI) */</span><br><span>diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c</span><br><span>index 28522a7..6b4cfda 100644</span><br><span>--- a/src/mainboard/amd/tilapia_fam10/mainboard.c</span><br><span>+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c</span><br><span>@@ -165,7 +165,7 @@</span><br><span> dword = pci_read_config32(sm_dev, 0xfc);</span><br><span> dword &= ~(1 << 10);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* When the gpio40 is configured as GPIO, this will represent the output value*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* When the gpio40 is configured as GPIO, this will represent the output value*/</span><br><span> /* 1 :enable two x8 , 0 : master slot enable only */</span><br><span> dword &= ~(1 << 26);</span><br><span> pci_write_config32(sm_dev, 0xfc, dword);</span><br><span>diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb</span><br><span>index 2ce1dfd..2b2cd9e 100644</span><br><span>--- a/src/mainboard/amd/torpedo/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/torpedo/devicetree.cb</span><br><span>@@ -62,7 +62,7 @@</span><br><span> end # kbc1100</span><br><span> end #LPC</span><br><span> device pci 14.4 on end # PCI bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.5 on end # USB 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # USB 2</span><br><span> device pci 14.6 on end # Ethernet Controller</span><br><span> device pci 14.7 on end # SD Flash Controller</span><br><span> device pci 15.0 on end # PCIe PortA</span><br><span>@@ -70,7 +70,7 @@</span><br><span> device pci 15.2 on end # PCIe PortC</span><br><span> device pci 15.3 on end # PCIe PortD</span><br><span> register "gpp_configuration" = "4" #1:1:1:1</span><br><span style="color: hsl(0, 100%, 40%);">- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE</span><br><span> end #southbridge/amd/cimx/sb900</span><br><span> device pci 18.0 on end</span><br><span> device pci 18.1 on end</span><br><span>diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl</span><br><span>index 5781754..ef7d1b0 100644</span><br><span>--- a/src/mainboard/amd/torpedo/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/torpedo/dsdt.asl</span><br><span>@@ -676,7 +676,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>@@ -691,13 +691,13 @@</span><br><span> * used, so it could be removed.</span><br><span> *</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * \_GTS OEM Going To Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_GTS OEM Going To Sleep method</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry:</span><br><span style="color: hsl(0, 100%, 40%);">- * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0=The value of the sleeping state S1=1, S2=2</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit:</span><br><span style="color: hsl(0, 100%, 40%);">- * -none-</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -none-</span><br><span> *</span><br><span> * Method(\_GTS, 1) {</span><br><span> * DBGO("\\_GTS\n")</span><br><span>@@ -766,7 +766,7 @@</span><br><span> } /* End Method(\_WAK) */</span><br><span> </span><br><span> Scope(\_GPE) { /* Start Scope GPE */</span><br><span style="color: hsl(0, 100%, 40%);">- } /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Scope GPE */</span><br><span> </span><br><span> /* System Bus */</span><br><span> Scope(\_SB) { /* Start \_SB scope */</span><br><span>diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c</span><br><span>index 5a77dc0..e26052a 100644</span><br><span>--- a/src/mainboard/amd/torpedo/gpio.c</span><br><span>+++ b/src/mainboard/amd/torpedo/gpio.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span> StripInfo = (Data8 & BIT7) >> 7;</span><br><span> Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);</span><br><span> StripInfo |= (Data8 & BIT7) >> 6;</span><br><span style="color: hsl(0, 100%, 40%);">- if (StripInfo < boardRevC) { // for old board. Rev B</span><br><span style="color: hsl(120, 100%, 40%);">+ if (StripInfo < boardRevC) { // for old board. Rev B</span><br><span> Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3</span><br><span> Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0</span><br><span> }</span><br><span>diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl</span><br><span>index 2f22758..30e6fdc 100644</span><br><span>--- a/src/mainboard/amd/union_station/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/amd/union_station/acpi/gpe.asl</span><br><span>@@ -72,7 +72,7 @@</span><br><span> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-} /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span> </span><br><span> /* Contains the GPEs for USB overcurrent */</span><br><span> #include "usb_oc.asl"</span><br><span>diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl</span><br><span>index d7cf365..ec38a8a 100644</span><br><span>--- a/src/mainboard/amd/union_station/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/amd/union_station/acpi/sleep.asl</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> /* On older chips, clear PciExpWakeDisEn */</span><br><span> /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">- * Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store(0,\_SB.PWDE)</span><br><span> *}</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl</span><br><span>index 299d4aa..6e9c701 100644</span><br><span>--- a/src/mainboard/amd/union_station/acpi/usb_oc.asl</span><br><span>+++ b/src/mainboard/amd/union_station/acpi/usb_oc.asl</span><br><span>@@ -36,7 +36,7 @@</span><br><span> </span><br><span> Method(UCOC, 0) {</span><br><span> Sleep(20)</span><br><span style="color: hsl(0, 100%, 40%);">- Store(0x13,CMTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x13,CMTI)</span><br><span> Store(0,GPSL)</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb</span><br><span>index d7d80ac..d290b8d 100644</span><br><span>--- a/src/mainboard/amd/union_station/devicetree.cb</span><br><span>+++ b/src/mainboard/amd/union_station/devicetree.cb</span><br><span>@@ -54,7 +54,7 @@</span><br><span> device pci 14.3 on # LPC 0x439d</span><br><span> end #LPC</span><br><span> device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.5 on end # USB 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # USB 2</span><br><span> device pci 15.0 off end # PCIe PortA</span><br><span> device pci 15.1 off end # PCIe PortB</span><br><span> device pci 15.2 off end # PCIe PortC</span><br><span>@@ -62,7 +62,7 @@</span><br><span> device pci 16.0 off end # OHCI USB3</span><br><span> device pci 16.2 off end # EHCI USB3</span><br><span> register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)</span><br><span style="color: hsl(0, 100%, 40%);">- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE</span><br><span> end #southbridge/amd/cimx/sb800</span><br><span> # end # device pci 18.0</span><br><span> # These seem unnecessary</span><br><span>diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c</span><br><span>index 8c71fd6..6848fed 100644</span><br><span>--- a/src/mainboard/amd/union_station/mainboard.c</span><br><span>+++ b/src/mainboard/amd/union_station/mainboard.c</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> </span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span> </span><br><span> /**********************************************</span><br><span> * Enable the dedicated functions of the board.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26607">change 26607</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26607"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3acc5b0c3895459a7aba53a422a978e31f652aa9 </div>
<div style="display:none"> Gerrit-Change-Number: 26607 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>