<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26630">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/lenovo: Get rid of whitespace before tab<br><br>Change-Id: I958fe66655cc3c589ce6709b83c56a9472628324<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/lenovo/g505s/acpi/gpe.asl<br>M src/mainboard/lenovo/g505s/acpi/sleep.asl<br>M src/mainboard/lenovo/g505s/buildOpts.c<br>M src/mainboard/lenovo/g505s/mainboard.h<br>4 files changed, 5 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26630/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl</span><br><span>index deecdc6..ace1d26 100644</span><br><span>--- a/src/mainboard/lenovo/g505s/acpi/gpe.asl</span><br><span>+++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl</span><br><span>@@ -73,4 +73,4 @@</span><br><span>                Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span>                Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span>     }</span><br><span style="color: hsl(0, 100%, 40%);">-}      /* End Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+}  /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl</span><br><span>index 947a2f2..d516cce 100644</span><br><span>--- a/src/mainboard/lenovo/g505s/acpi/sleep.asl</span><br><span>+++ b/src/mainboard/lenovo/g505s/acpi/sleep.asl</span><br><span>@@ -44,7 +44,7 @@</span><br><span> </span><br><span>         /* On older chips, clear PciExpWakeDisEn */</span><br><span>  /*if (LLessEqual(\_SB.SBRI, 0x13)) {</span><br><span style="color: hsl(0, 100%, 40%);">-    *       Store(0,\_SB.PWDE)</span><br><span style="color: hsl(120, 100%, 40%);">+    *       Store(0,\_SB.PWDE)</span><br><span>   *}</span><br><span>   */</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c</span><br><span>index 3e28a30..4919036 100644</span><br><span>--- a/src/mainboard/lenovo/g505s/buildOpts.c</span><br><span>+++ b/src/mainboard/lenovo/g505s/buildOpts.c</span><br><span>@@ -171,8 +171,8 @@</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span> #define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED</span><br><span> #define BLDCFG_UMA_ALLOCATION_MODE             UMA_SPECIFIED</span><br><span style="color: hsl(0, 100%, 40%);">-//#define BLDCFG_UMA_ALLOCATION_SIZE               0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDCFG_UMA_ALLOCATION_SIZE         0x2000//512M</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_UMA_ALLOCATION_SIZE      0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_SIZE       0x2000//512M</span><br><span> #define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h</span><br><span>index 49aaedd..bfa27b4 100644</span><br><span>--- a/src/mainboard/lenovo/g505s/mainboard.h</span><br><span>+++ b/src/mainboard/lenovo/g505s/mainboard.h</span><br><span>@@ -17,7 +17,7 @@</span><br><span> /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but</span><br><span>  * we make the distinction between GEVENT pin and SCI.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_SCI_GPE          EC_SCI_GEVENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPE               EC_SCI_GEVENT</span><br><span> #define EC_LID_GPE             EC_LID_GEVENT</span><br><span> #define PME_GPE                        0x0b</span><br><span> #define PCIE_GPE                0x18</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26630">change 26630</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26630"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I958fe66655cc3c589ce6709b83c56a9472628324 </div>
<div style="display:none"> Gerrit-Change-Number: 26630 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>