<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/26544">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Philipp Deppenwiese: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation: More markdown fixes after switching to sphinx<br><br>Fix markdown code to work with sphinx.<br><br>Change-Id: I52014494dc2d09731fe14ab527073352ada860d1<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>Reviewed-on: https://review.coreboot.org/26544<br>Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md<br>M Documentation/Intel/NativeRaminit/Sandybridge_freq.md<br>M Documentation/Intel/NativeRaminit/Sandybridge_read.md<br>3 files changed, 50 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md</span><br><span>index 477c559..ab0b513 100644</span><br><span>--- a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md</span><br><span>+++ b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md</span><br><span>@@ -10,15 +10,15 @@</span><br><span> </span><br><span> The multi-processor initialization code has to take care of lots of duties:</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-1 Bringing all cores out of reset</span><br><span style="color: hsl(0, 100%, 40%);">-2 Load latest microcode on all cores</span><br><span style="color: hsl(0, 100%, 40%);">-3 Sync latest MTRR snapshot between BSP and APs</span><br><span style="color: hsl(0, 100%, 40%);">-4 Perform sets of CPU feature programming</span><br><span style="color: hsl(0, 100%, 40%);">- * CPU Power & Thermal Management</span><br><span style="color: hsl(0, 100%, 40%);">- * Overclocking</span><br><span style="color: hsl(0, 100%, 40%);">- * Intel Trusted Execution Technology</span><br><span style="color: hsl(0, 100%, 40%);">- * Intel Software Guard Extensions</span><br><span style="color: hsl(0, 100%, 40%);">- * Intel Processor Trace etc.</span><br><span style="color: hsl(120, 100%, 40%);">+1. Bringing all cores out of reset</span><br><span style="color: hsl(120, 100%, 40%);">+2. Load latest microcode on all cores</span><br><span style="color: hsl(120, 100%, 40%);">+3. Sync latest MTRR snapshot between BSP and APs</span><br><span style="color: hsl(120, 100%, 40%);">+4. Perform sets of CPU feature programming</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPU Power & Thermal Management</span><br><span style="color: hsl(120, 100%, 40%);">+ * Overclocking</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Trusted Execution Technology</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Software Guard Extensions</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Processor Trace etc.</span><br><span> </span><br><span> This above CPU feature programming lists are expected to grow with current and future</span><br><span> CPU complexity and there might be some cases where certain feature programming mightbe</span><br><span>@@ -39,30 +39,39 @@</span><br><span> Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate</span><br><span> PPI to perform certain API call, hence coreboot has to created MP services APIs known as</span><br><span> EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.</span><br><span style="color: hsl(0, 100%, 40%);">-More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+More details here: [PI_Spec_1_6]</span><br><span> </span><br><span> ### coreboot to publish EFI_MP_SERVICES_PPI APIs</span><br><span style="color: hsl(0, 100%, 40%);">-| API | Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|------------------------------|------------------------------------------------------------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiGetNumberOfProcessors | Get the number of CPU's. |</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiGetProcessorInfo | Get information on a specific CPU. |</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiStartupAllAPs | Activate all of the application processors. |</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiStartupThisAP | Activate a specific application processor. |</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiSwitchBSP | Switch the boot strap processor. |</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiEnableDisableAP | Enable or disable an application processor. |</span><br><span style="color: hsl(0, 100%, 40%);">-| PeiWhoAmI | Identify the currently executing processor. |</span><br><span style="color: hsl(0, 100%, 40%);">-|------------------------------|------------------------------------------------------------------|</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| API | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++==============================+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiGetNumberOfProcessors | Get the number of CPU's. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiGetProcessorInfo | Get information on a specific CPU. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiStartupAllAPs | Activate all of the application processors. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiStartupThisAP | Activate a specific application processor. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiSwitchBSP | Switch the boot strap processor. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiEnableDisableAP | Enable or disable an application processor. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiWhoAmI | Identify the currently executing processor. |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------------------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> ## Code Flow</span><br><span> </span><br><span> Here is proposed design flow with coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make</span><br><span> use of the same to perform some CPU feature programming.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-** coreboot-FSP MP init flow **</span><br><span style="color: hsl(0, 100%, 40%);">-![alt text][coreboot_publish_mp_service_api]</span><br><span style="color: hsl(120, 100%, 40%);">+**coreboot-FSP MP init flow**</span><br><span style="color: hsl(120, 100%, 40%);">+![coreboot-fsp mp init flow][coreboot_publish_mp_service_api]</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png "coreboot-fsp mp init flow"</span><br><span style="color: hsl(120, 100%, 40%);">+[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png</span><br><span> </span><br><span> ## Benefits</span><br><span> 1. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.</span><br><span>@@ -72,3 +81,5 @@</span><br><span> coreboot interfaces to execute those programming.</span><br><span> 3. coreboot will have more control over running those feature programming as API optimization</span><br><span> handled by coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[PI_Spec_1_6]: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf</span><br><span>diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md</span><br><span>index cf68d5e..d8b73b3 100644</span><br><span>--- a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md</span><br><span>+++ b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md</span><br><span>@@ -69,7 +69,7 @@</span><br><span> </span><br><span> > **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-## <a name="hard_fuses"></a> Hard fuses</span><br><span style="color: hsl(120, 100%, 40%);">+## Hard fuses</span><br><span> "Hard" fuses are programmed by Intel and limit the maximum frequency that can</span><br><span> be used on a given CPU/board/chipset. At time of writing there's no register</span><br><span> to read this limit, before trying to set a given DRAM frequency. The memory PLL</span><br><span>@@ -77,8 +77,8 @@</span><br><span> this case coreboot tries the next smaller memory multiplier until the PLL will</span><br><span> lock.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-## <a name="devicetree"></a> Devicetree</span><br><span style="color: hsl(0, 100%, 40%);">-The devicetree register ```max_mem_clock_mhz``` overrides the "soft" fuses set</span><br><span style="color: hsl(120, 100%, 40%);">+## Devicetree</span><br><span style="color: hsl(120, 100%, 40%);">+The devicetree register `max_mem_clock_mhz` overrides the "soft" fuses set</span><br><span> by the board manufacturer.</span><br><span> </span><br><span> By using this register it's possible to force a minimum operating frequency.</span><br><span>diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_read.md b/Documentation/Intel/NativeRaminit/Sandybridge_read.md</span><br><span>index e58298a..0496657 100644</span><br><span>--- a/Documentation/Intel/NativeRaminit/Sandybridge_read.md</span><br><span>+++ b/Documentation/Intel/NativeRaminit/Sandybridge_read.md</span><br><span>@@ -78,20 +78,20 @@</span><br><span> on the left-hand side has zero IO delay.</span><br><span> </span><br><span> #### roundtrip 55 DCKs</span><br><span style="color: hsl(0, 100%, 40%);">-![alt text][timA_lane0-3_rt55]</span><br><span style="color: hsl(120, 100%, 40%);">+![timA for lane0 - lane3, roundtrip 55][timA_lane0-3_rt55]</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-[timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"</span><br><span style="color: hsl(120, 100%, 40%);">+[timA_lane0-3_rt55]: timA_lane0-3_rt55.png</span><br><span> </span><br><span> #### roundtrip 54 DCKs</span><br><span style="color: hsl(0, 100%, 40%);">-![alt text][timA_lane0-3_rt54]</span><br><span style="color: hsl(120, 100%, 40%);">+![timA for lane0 - lane3, roundtrip 54][timA_lane0-3_rt54]</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-[timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"</span><br><span style="color: hsl(120, 100%, 40%);">+[timA_lane0-3_rt54]: timA_lane0-3_rt54.png</span><br><span> </span><br><span> </span><br><span> #### roundtrip 53 DCKs</span><br><span style="color: hsl(0, 100%, 40%);">-![alt text][timA_lane0-3_rt53]</span><br><span style="color: hsl(120, 100%, 40%);">+![timA for lane0 - lane3, roundtrip 53][timA_lane0-3_rt53]</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-[timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"</span><br><span style="color: hsl(120, 100%, 40%);">+[timA_lane0-3_rt53]: timA_lane0-3_rt53.png</span><br><span> </span><br><span> As you can see the signal has some jitter as every sample was taken in a</span><br><span> different loop iteration. The result register only contains a single bit per</span><br><span>@@ -128,13 +128,13 @@</span><br><span> The roundtrip time and IO delay will be adjusted until all lanes are aligned.</span><br><span> The resulting IO delay is visible in the picture below.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-** roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs **</span><br><span style="color: hsl(0, 100%, 40%);">-![alt text][timA_lane0-3_discover_420x]</span><br><span style="color: hsl(120, 100%, 40%);">+**roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs**</span><br><span style="color: hsl(120, 100%, 40%);">+![timA for lane0 - lane3, finding minimum roundtrip time][timA_lane0-3_discover_420x]</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png "timA for lane0 - lane3, finding minimum roundtrip time"</span><br><span style="color: hsl(120, 100%, 40%);">+[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-** Note: The sampled data has been shifted by timA. The preamble is now</span><br><span style="color: hsl(0, 100%, 40%);">-in phase. **</span><br><span style="color: hsl(120, 100%, 40%);">+**Note: The sampled data has been shifted by timA. The preamble is now</span><br><span style="color: hsl(120, 100%, 40%);">+in phase.**</span><br><span> </span><br><span> ## Fine adjustment</span><br><span> </span><br><span>@@ -146,8 +146,8 @@</span><br><span> the falling edge of the preamble) to get the final IO phase. You can see the</span><br><span> result in the picture below.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-![alt text][timA_lane0-3_adjust_fine]</span><br><span style="color: hsl(120, 100%, 40%);">+![timA for lane0 - lane3, fine adjustment][timA_lane0-3_adjust_fine]</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png "timA for lane0 - lane3, fine adjustment"</span><br><span style="color: hsl(120, 100%, 40%);">+[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png</span><br><span> </span><br><span> Lanes 0 - 2 will be adjusted by a phase of -10, while lane 3 is already correct.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26544">change 26544</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26544"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I52014494dc2d09731fe14ab527073352ada860d1 </div>
<div style="display:none"> Gerrit-Change-Number: 26544 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>