<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26626">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel: Get rid of whitespace before tab<br><br>Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/intel/baskingridge/acpi/superio.asl<br>M src/mainboard/intel/bayleybay_fsp/irqroute.h<br>M src/mainboard/intel/d945gclf/acpi/thermal.asl<br>M src/mainboard/intel/d945gclf/devicetree.cb<br>M src/mainboard/intel/dg41wv/devicetree.cb<br>M src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl<br>M src/mainboard/intel/emeraldlake2/acpi/superio.asl<br>M src/mainboard/intel/kunimitsu/gpio.h<br>M src/mainboard/intel/littleplains/irqroute.h<br>M src/mainboard/intel/mohonpeak/irqroute.h<br>M src/mainboard/intel/saddlebrook/gpio.h<br>11 files changed, 60 insertions(+), 60 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26626/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/baskingridge/acpi/superio.asl b/src/mainboard/intel/baskingridge/acpi/superio.asl</span><br><span>index d99b22e..7944d9f 100644</span><br><span>--- a/src/mainboard/intel/baskingridge/acpi/superio.asl</span><br><span>+++ b/src/mainboard/intel/baskingridge/acpi/superio.asl</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller</span><br><span> #define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60</span><br><span> #define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO</span><br><span> #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60</span><br><span> #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h</span><br><span>index a24be3e..41b990b 100644</span><br><span>--- a/src/mainboard/intel/bayleybay_fsp/irqroute.h</span><br><span>+++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h</span><br><span>@@ -20,14 +20,14 @@</span><br><span> #include <soc/intel/fsp_baytrail/include/soc/pci_devs.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- *IR02h GFX INT(A) - PIRQ A</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR02h GFX INT(A) - PIRQ A</span><br><span> *IR10h EMMC INT(ABCD) - PIRQ DEFG</span><br><span style="color: hsl(0, 100%, 40%);">- *IR11h SDIO INT(A) - PIRQ B</span><br><span style="color: hsl(0, 100%, 40%);">- *IR12h SD INT(A) - PIRQ C</span><br><span style="color: hsl(0, 100%, 40%);">- *IR13h SATA INT(A) - PIRQ D</span><br><span style="color: hsl(0, 100%, 40%);">- *IR14h XHCI INT(A) - PIRQ E</span><br><span style="color: hsl(0, 100%, 40%);">- *IR15h LP Audio INT(A) - PIRQ F</span><br><span style="color: hsl(0, 100%, 40%);">- *IR17h MMC INT(A) - PIRQ F</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR11h SDIO INT(A) - PIRQ B</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR12h SD INT(A) - PIRQ C</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR13h SATA INT(A) - PIRQ D</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR14h XHCI INT(A) - PIRQ E</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR15h LP Audio INT(A) - PIRQ F</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR17h MMC INT(A) - PIRQ F</span><br><span> *IR18h SIO INT(ABCD) - PIRQ BADC</span><br><span> *IR1Ah TXE INT(A) - PIRQ F</span><br><span> *IR1Bh HD Audio INT(A) - PIRQ G</span><br><span>diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl</span><br><span>index 589023f..27337d4 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/acpi/thermal.asl</span><br><span>+++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl</span><br><span>@@ -36,7 +36,7 @@</span><br><span> </span><br><span> // Method (_AC1, 0, Serialized)</span><br><span> // {</span><br><span style="color: hsl(0, 100%, 40%);">- // Return (0xf5c)</span><br><span style="color: hsl(120, 100%, 40%);">+ // Return (0xf5c)</span><br><span> // }</span><br><span> </span><br><span> // Critical shutdown temperature</span><br><span>diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb</span><br><span>index e8c2792..f3c37b2 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/d945gclf/devicetree.cb</span><br><span>@@ -54,19 +54,19 @@</span><br><span> register "c3_latency" = "85"</span><br><span> register "p_cnt_throttling_supported" = "0"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1b.0 on end # High Definition Audio</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 on end # PCIe</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.1 on end # PCIe</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.2 on end # PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # High Definition Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on end # PCIe</span><br><span> #device pci 1c.3 off end # PCIe port 4</span><br><span> #device pci 1c.4 off end # PCIe port 5</span><br><span> #device pci 1c.5 off end # PCIe port 6</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.0 on end # USB UHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.1 on end # USB UHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.2 on end # USB UHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 on end # USB UHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.7 on end # USB2 EHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # USB UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # USB UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # USB UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on end # USB2 EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span> #device pci 1e.2 off end # AC'97 Audio</span><br><span> #device pci 1e.3 off end # AC'97 Modem</span><br><span> device pci 1f.0 on # LPC bridge</span><br><span>diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb</span><br><span>index 214c49b..d96ad95 100644</span><br><span>--- a/src/mainboard/intel/dg41wv/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/dg41wv/devicetree.cb</span><br><span>@@ -154,7 +154,7 @@</span><br><span> end</span><br><span> end</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.1 off end # PATA/IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 off end # PATA/IDE</span><br><span> device pci 1f.2 on # SATA</span><br><span> subsystemid 0x8086 0x5756</span><br><span> end</span><br><span>diff --git a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl</span><br><span>index 8e56679..a0e7f07 100644</span><br><span>--- a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl</span><br><span>+++ b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl</span><br><span>@@ -32,7 +32,7 @@</span><br><span> /* ?? */</span><br><span> Package() { 0x0016ffff, 0, 0, 0x12 },</span><br><span> Package() { 0x0016ffff, 1, 0, 0x13 },</span><br><span style="color: hsl(0, 100%, 40%);">- /* GBE 0:19.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GBE 0:19.0 */</span><br><span> Package() { 0x0019ffff, 0, 0, 0x10 },</span><br><span> /* USB and EHCI */</span><br><span> Package() { 0x001affff, 0, 0, 0x10 },</span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl</span><br><span>index d99b22e..7944d9f 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller</span><br><span> #define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60</span><br><span> #define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO</span><br><span> #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60</span><br><span> #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h</span><br><span>index 721c74c..e9d0495 100644</span><br><span>--- a/src/mainboard/intel/kunimitsu/gpio.h</span><br><span>+++ b/src/mainboard/intel/kunimitsu/gpio.h</span><br><span>@@ -81,15 +81,15 @@</span><br><span> /* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),</span><br><span> /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span> /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span> /* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),</span><br><span> /* ISH_GP1 */ PAD_CFG_NC(GPP_A19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),</span><br><span> /* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),</span><br><span> /* GYRO_INT */ PAD_CFG_NC(GPP_A22),</span><br><span> /* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span> /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),</span><br><span> /* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),</span><br><span> /* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),</span><br><span>@@ -100,10 +100,10 @@</span><br><span> /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span> /* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),</span><br><span> /* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span> /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span> /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),</span><br><span> /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),</span><br><span> /* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),</span><br><span> /* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),</span><br><span>@@ -111,10 +111,10 @@</span><br><span> /* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),</span><br><span> /* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),</span><br><span> /* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),</span><br><span> /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span> /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),</span><br><span> /* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),</span><br><span> /* SML0DATA */ PAD_CFG_NC(GPP_C4),</span><br><span> /* SML0ALERT# */ PAD_CFG_NC(GPP_C5),</span><br><span>@@ -145,7 +145,7 @@</span><br><span> /* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),</span><br><span> /* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span> /* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),</span><br><span> /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP),</span><br><span> /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP),</span><br><span> /* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),</span><br><span>@@ -162,17 +162,17 @@</span><br><span> /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span> /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),</span><br><span> /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),</span><br><span> /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),</span><br><span> /* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),</span><br><span> /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),</span><br><span> /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),</span><br><span> /* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),</span><br><span> /* SATALED# */ PAD_CFG_NC(GPP_E8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span> /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),</span><br><span> /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),</span><br><span> /* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),</span><br><span>@@ -185,8 +185,8 @@</span><br><span> </span><br><span> /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),</span><br><span> /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),</span><br><span> /* I2S2_TXD */ PAD_CFG_NC(GPP_F2),</span><br><span> /* I2S2_RXD */ PAD_CFG_NC(GPP_F3),</span><br><span> /* I2C2_SDA */ PAD_CFG_NC(GPP_F4),</span><br><span>@@ -195,8 +195,8 @@</span><br><span> /* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span> /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span> /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">-/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),</span><br><span> /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),</span><br><span> /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),</span><br><span> /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),</span><br><span>@@ -225,7 +225,7 @@</span><br><span> /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),</span><br><span> /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),</span><br><span> /* GPD7 */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span> /* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),</span><br><span> /* PM_SLP_S5# */ PAD_CFG_NC(GPD10),</span><br><span> /* LANPHYC */ PAD_CFG_NC(GPD11),</span><br><span>diff --git a/src/mainboard/intel/littleplains/irqroute.h b/src/mainboard/intel/littleplains/irqroute.h</span><br><span>index 5f0794a..eb44fde 100644</span><br><span>--- a/src/mainboard/intel/littleplains/irqroute.h</span><br><span>+++ b/src/mainboard/intel/littleplains/irqroute.h</span><br><span>@@ -21,10 +21,10 @@</span><br><span> #include <southbridge/intel/fsp_rangeley/pci_devs.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IR01h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(0, 100%, 40%);">- * IR02h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(0, 100%, 40%);">- * IR03h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(0, 100%, 40%);">- * IR04h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR01h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR02h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR03h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR04h PCIe INT(ABCD) - PIRQ ABCD</span><br><span> * IR0Bh IQIA INT(ABCD) - PIRQ EFGH</span><br><span> * IR0Eh RAS INT(A) - PIRQ A</span><br><span> * IR13h SMBUS1 INT(A) - PIRQ B</span><br><span>diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h</span><br><span>index 913ae52..43a69d9 100644</span><br><span>--- a/src/mainboard/intel/mohonpeak/irqroute.h</span><br><span>+++ b/src/mainboard/intel/mohonpeak/irqroute.h</span><br><span>@@ -21,10 +21,10 @@</span><br><span> #include <southbridge/intel/fsp_rangeley/pci_devs.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IR01h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(0, 100%, 40%);">- * IR02h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(0, 100%, 40%);">- * IR03h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(0, 100%, 40%);">- * IR04h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR01h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR02h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR03h PCIe INT(ABCD) - PIRQ ABCD</span><br><span style="color: hsl(120, 100%, 40%);">+ * IR04h PCIe INT(ABCD) - PIRQ ABCD</span><br><span> * IR0Bh IQIA INT(ABCD) - PIRQ EFGH</span><br><span> * IR0Eh RAS INT(A) - PIRQ A</span><br><span> * IR13h SMBUS1 INT(A) - PIRQ B</span><br><span>diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h</span><br><span>index 62c57cb..98feea2 100644</span><br><span>--- a/src/mainboard/intel/saddlebrook/gpio.h</span><br><span>+++ b/src/mainboard/intel/saddlebrook/gpio.h</span><br><span>@@ -239,17 +239,17 @@</span><br><span> /* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),</span><br><span> /* TBD */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),</span><br><span> </span><br><span> /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span> /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26626">change 26626</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26626"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa </div>
<div style="display:none"> Gerrit-Change-Number: 26626 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>