<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26579">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel: Use postcar_frame_add_romcache()<br><br>Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/northbridge/intel/gm45/ram_calc.c<br>M src/northbridge/intel/i945/ram_calc.c<br>M src/northbridge/intel/nehalem/ram_calc.c<br>M src/northbridge/intel/pineview/ram_calc.c<br>M src/northbridge/intel/sandybridge/ram_calc.c<br>M src/northbridge/intel/x4x/ram_calc.c<br>6 files changed, 6 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/26579/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 9b70523..71b5863 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -129,8 +129,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 076744f..bc5f9c8 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -91,8 +91,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span>diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c</span><br><span>index 93d1ccf..bbf84f9 100644</span><br><span>--- a/src/northbridge/intel/nehalem/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/nehalem/ram_calc.c</span><br><span>@@ -50,8 +50,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span>diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>index e98ad71..fd893bc 100644</span><br><span>--- a/src/northbridge/intel/pineview/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>@@ -118,8 +118,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span>diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>index c76e4be..cf583c03 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>@@ -57,8 +57,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span>diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>index 6c05efd..d5743e3 100644</span><br><span>--- a/src/northbridge/intel/x4x/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>@@ -116,8 +116,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26579">change 26579</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e </div>
<div style="display:none"> Gerrit-Change-Number: 26579 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>