<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26588">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/fsp_baytrail: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/fsp_baytrail/acpi.c<br>M src/soc/intel/fsp_baytrail/chip.c<br>M src/soc/intel/fsp_baytrail/cpu.c<br>M src/soc/intel/fsp_baytrail/gfx.c<br>M src/soc/intel/fsp_baytrail/i2c.c<br>M src/soc/intel/fsp_baytrail/include/soc/acpi.h<br>M src/soc/intel/fsp_baytrail/include/soc/baytrail.h<br>M src/soc/intel/fsp_baytrail/include/soc/ramstage.h<br>M src/soc/intel/fsp_baytrail/lpe.c<br>M src/soc/intel/fsp_baytrail/lpss.c<br>M src/soc/intel/fsp_baytrail/northcluster.c<br>M src/soc/intel/fsp_baytrail/ramstage.c<br>M src/soc/intel/fsp_baytrail/southcluster.c<br>13 files changed, 50 insertions(+), 50 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/26588/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c</span><br><span>index 0156816..7ce1b35 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/acpi.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/acpi.c</span><br><span>@@ -499,7 +499,7 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void generate_cpu_entries(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void generate_cpu_entries(struct device *device)</span><br><span> {</span><br><span> int core;</span><br><span> int pcontrol_blk = get_pmbase(), plen = 6;</span><br><span>@@ -553,7 +553,7 @@</span><br><span> return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southcluster_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southcluster_write_acpi_tables(struct device *device,</span><br><span> unsigned long current,</span><br><span> struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>@@ -581,7 +581,7 @@</span><br><span> return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_inject_dsdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_inject_dsdt(struct device *device)</span><br><span> {</span><br><span> global_nvs_t *gnvs;</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c</span><br><span>index 814417a..a041b81 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/chip.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/chip.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include <drivers/intel/fsp1_0/fsp_util.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span> assign_resources(dev->link_list);</span><br><span> }</span><br><span>@@ -42,7 +42,7 @@</span><br><span> .scan_bus = NULL,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",</span><br><span> dev_name(dev), dev->path.type);</span><br><span>@@ -73,7 +73,7 @@</span><br><span> .init = soc_init,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>index 38c4446..c7694b9 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void baytrail_core_init(device_t cpu)</span><br><span style="color: hsl(120, 100%, 40%);">+static void baytrail_core_init(struct device *cpu)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Init BayTrail core.\n");</span><br><span> </span><br><span>@@ -164,7 +164,7 @@</span><br><span> .post_mp_init = enable_smis,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void baytrail_init_cpus(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void baytrail_init_cpus(struct device *dev)</span><br><span> {</span><br><span> struct bus *cpu_bus = dev->link_list;</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c</span><br><span>index 62224fa..5464b66 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/gfx.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/gfx.c</span><br><span>@@ -74,24 +74,24 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)</span><br><span> {</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_pre_vbios_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_pre_vbios_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");</span><br><span> gfx_run_script(dev, gpu_pre_vbios_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_post_vbios_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_post_vbios_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_INFO, "GFX: Post VBIOS Init\n");</span><br><span> gfx_run_script(dev, gfx_post_vbios_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_init(struct device *dev)</span><br><span> {</span><br><span> /* Pre VBIOS Init */</span><br><span> gfx_pre_vbios_init(dev);</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c</span><br><span>index 4565ba4..95761f3 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/i2c.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/i2c.c</span><br><span>@@ -100,7 +100,7 @@</span><br><span> */</span><br><span> int i2c_init(unsigned bus)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE,</span><br><span> I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE,</span><br><span> I2C6_MEM_BASE};</span><br><span>@@ -166,7 +166,7 @@</span><br><span> {</span><br><span> int i = 0;</span><br><span> char *base_ptr = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> unsigned int val;</span><br><span> int stat;</span><br><span> </span><br><span>@@ -225,7 +225,7 @@</span><br><span> {</span><br><span> int i;</span><br><span> char *base_ptr;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> unsigned int val;</span><br><span> int stat;</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h</span><br><span>index 388ebc2..27b7000 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/acpi.h</span><br><span>@@ -28,10 +28,10 @@</span><br><span> void acpi_init_gnvs(global_nvs_t *gnvs);</span><br><span> </span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southcluster_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southcluster_write_acpi_tables(struct device *device,</span><br><span> unsigned long current,</span><br><span> struct acpi_rsdp *rsdp);</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_inject_dsdt(device_t device);</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_inject_dsdt(struct device *device);</span><br><span> #endif</span><br><span> </span><br><span> #endif /* _BAYTRAIL_ACPI_H_ */</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h</span><br><span>index bc75567..82fd0a1 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h</span><br><span>@@ -56,7 +56,7 @@</span><br><span> int soc_silicon_revision(void);</span><br><span> int soc_silicon_type(void);</span><br><span> int soc_silicon_supported(int type, int rev);</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_enable(struct device *dev);</span><br><span> </span><br><span> /* debugging functions */</span><br><span> void print_pci_devices(void);</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h</span><br><span>index 5c2f98a..e8f81bb 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h</span><br><span>@@ -21,10 +21,10 @@</span><br><span> /* The baytrail_init_pre_device() function is called prior to device</span><br><span> * initialization, but it's after console and cbmem has been reinitialized. */</span><br><span> void baytrail_init_pre_device(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void baytrail_init_cpus(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void baytrail_init_cpus(struct device *dev);</span><br><span> void set_max_freq(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_enable_dev(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_enable_dev(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);</span><br><span> </span><br><span> extern struct pci_operations soc_pci_ops;</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c</span><br><span>index 4fbdce1..84a10fd 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/lpe.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/lpe.c</span><br><span>@@ -41,7 +41,7 @@</span><br><span> #define FIRMWARE_REG_BASE_C0 0x144000</span><br><span> #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -50,7 +50,7 @@</span><br><span> *field = res->base;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_enable_acpi_mode(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_enable_acpi_mode(struct device *dev)</span><br><span> {</span><br><span> static const struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>@@ -83,7 +83,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void setup_codec_clock(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_codec_clock(struct device *dev)</span><br><span> {</span><br><span> uint32_t reg;</span><br><span> u32 *clk_reg;</span><br><span>@@ -121,7 +121,7 @@</span><br><span> write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_stash_firmware_info(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_stash_firmware_info(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct resource *mmio;</span><br><span>@@ -147,7 +147,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_fsp_baytrail_config *config = dev->chip_info;</span><br><span> </span><br><span>@@ -159,7 +159,7 @@</span><br><span> lpe_enable_acpi_mode(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_read_resources(struct device *dev)</span><br><span> {</span><br><span> pci_dev_read_resources(dev);</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c</span><br><span>index 427fc6d..8820eed 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/lpss.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/lpss.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)</span><br><span> {</span><br><span> struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>@@ -66,7 +66,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)</span><br><span> {</span><br><span> struct reg_script ops[] = {</span><br><span> REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,</span><br><span>@@ -78,7 +78,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)</span><br><span> {</span><br><span> *iosf_reg = -1;</span><br><span> *nvs_index = -1;</span><br><span>@@ -119,7 +119,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i2c_disable_resets(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i2c_disable_resets(struct device *dev)</span><br><span> {</span><br><span> /* Release the I2C devices from reset. */</span><br><span> static const struct reg_script ops[] = {</span><br><span>@@ -146,7 +146,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpss_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpss_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_fsp_baytrail_config *config = dev->chip_info;</span><br><span> int iosf_reg, nvs_index;</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c</span><br><span>index b4aceee..9f22b25 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/northcluster.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/northcluster.c</span><br><span>@@ -88,7 +88,7 @@</span><br><span> </span><br><span> static int get_pcie_bar(u32 *base)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> u32 pciexbar_reg;</span><br><span> </span><br><span> *base = 0;</span><br><span>@@ -123,7 +123,7 @@</span><br><span> return index;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_add_dram_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_add_dram_resources(struct device *dev)</span><br><span> {</span><br><span> u32 bmbound, bsmmrrl;</span><br><span> int index = 0;</span><br><span>@@ -166,7 +166,7 @@</span><br><span> index = add_fixed_resources(dev, index);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void nc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void nc_read_resources(struct device *dev)</span><br><span> {</span><br><span> u32 pcie_config_base;</span><br><span> int buses;</span><br><span>@@ -185,7 +185,7 @@</span><br><span> mc_add_dram_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void nc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void nc_enable(struct device *dev)</span><br><span> {</span><br><span> print_fsp_info();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>index a322ee3..fc50e64 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>@@ -73,7 +73,7 @@</span><br><span> </span><br><span> static void fill_in_pattrs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> msr_t msr;</span><br><span> struct pattrs *attrs = (struct pattrs *)pattrs_get();</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c</span><br><span>index a547152..6fa2192 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/southcluster.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/southcluster.c</span><br><span>@@ -50,12 +50,12 @@</span><br><span> typedef struct soc_intel_fsp_baytrail_config config_t;</span><br><span> </span><br><span> static inline void</span><br><span style="color: hsl(0, 100%, 40%);">-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)</span><br><span style="color: hsl(120, 100%, 40%);">+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)</span><br><span> {</span><br><span> mmio_resource(dev, i, addr >> 10, size >> 10);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span> add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);</span><br><span> add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);</span><br><span>@@ -167,8 +167,8 @@</span><br><span> */</span><br><span> static void write_pci_config_irqs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t irq_dev;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t targ_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *targ_dev;</span><br><span> uint8_t int_line = 0;</span><br><span> uint8_t original_int_pin = 0;</span><br><span> uint8_t new_int_pin = 0;</span><br><span>@@ -261,7 +261,7 @@</span><br><span> printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_pirq_init(struct device *dev)</span><br><span> {</span><br><span> int i, j;</span><br><span> int pirq;</span><br><span>@@ -324,7 +324,7 @@</span><br><span> * Note: this function assumes there is no overlap with the default LPC device's</span><br><span> * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_io_resource(device_t dev, int base, int size, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_io_resource(struct device *dev, int base, int size, int index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -338,7 +338,7 @@</span><br><span> IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_io_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_io_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> u8 io_index = 0;</span><br><span>@@ -360,7 +360,7 @@</span><br><span> sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_read_resources(struct device *dev)</span><br><span> {</span><br><span> /* Get the normal PCI resources of this device. */</span><br><span> pci_dev_read_resources(dev);</span><br><span>@@ -415,7 +415,7 @@</span><br><span> */</span><br><span> </span><br><span> /* Set bit in function disable register to hide this device. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_disable_devfn(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_disable_devfn(struct device *dev)</span><br><span> {</span><br><span> u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);</span><br><span> u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);</span><br><span>@@ -463,7 +463,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_d3hot_bits(device_t dev, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_d3hot_bits(struct device *dev, int offset)</span><br><span> {</span><br><span> uint32_t reg8;</span><br><span> printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);</span><br><span>@@ -475,7 +475,7 @@</span><br><span> /* Parts of the audio subsystem are powered by the HDA device. Therefore, one</span><br><span> * cannot put HDA into D3Hot. Instead perform this workaround to make some of</span><br><span> * the audio paths work for LPE audio. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void hda_work_around(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hda_work_around(struct device *dev)</span><br><span> {</span><br><span> u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);</span><br><span> </span><br><span>@@ -492,7 +492,7 @@</span><br><span> pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int place_device_in_d3hot(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int place_device_in_d3hot(struct device *dev)</span><br><span> {</span><br><span> unsigned offset;</span><br><span> </span><br><span>@@ -569,7 +569,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Common PCI device function disable. */</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_enable_dev(struct device *dev)</span><br><span> {</span><br><span> uint32_t reg32;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26588">change 26588</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26588"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072 </div>
<div style="display:none"> Gerrit-Change-Number: 26588 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>