<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26574">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">{cpu,drivers,nb}/intel: Use CACHE_ROM_BASE where appropriate<br><br>Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/cpu/intel/car/romstage.c<br>M src/cpu/intel/fsp_model_406dx/bootblock.c<br>M src/drivers/intel/fsp1_0/cache_as_ram.inc<br>M src/northbridge/intel/gm45/ram_calc.c<br>M src/northbridge/intel/i945/ram_calc.c<br>M src/northbridge/intel/nehalem/ram_calc.c<br>M src/northbridge/intel/pineview/ram_calc.c<br>M src/northbridge/intel/sandybridge/ram_calc.c<br>M src/northbridge/intel/x4x/ram_calc.c<br>9 files changed, 9 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/26574/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c</span><br><span>index 555c384..03a94ee 100644</span><br><span>--- a/src/cpu/intel/car/romstage.c</span><br><span>+++ b/src/cpu/intel/car/romstage.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span> postcar_frame_init_lowmem(&pcf);</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c</span><br><span>index a208ec9..327c4a4 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/bootblock.c</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c</span><br><span>@@ -62,8 +62,7 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> disable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1,</span><br><span style="color: hsl(0, 100%, 40%);">- CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span> enable_cache();</span><br><span> </span><br><span> /* Enable Variable MTRRs */</span><br><span>diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc</span><br><span>index eb21348..d08f582 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc</span><br><span>+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc</span><br><span>@@ -112,7 +112,7 @@</span><br><span> CAR_init_params:</span><br><span> .long dummy_microcode</span><br><span> .long 0</span><br><span style="color: hsl(0, 100%, 40%);">- .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CACHE_ROM_BASE /* Firmware Location */</span><br><span> .long CACHE_ROM_SIZE /* Total Firmware Length */</span><br><span> </span><br><span> CAR_init_stack:</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 1e434c7..9b70523 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -129,7 +129,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 990df97..076744f 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -91,7 +91,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span>diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c</span><br><span>index 37c1ed3..93d1ccf 100644</span><br><span>--- a/src/northbridge/intel/nehalem/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/nehalem/ram_calc.c</span><br><span>@@ -50,7 +50,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span>diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>index 63f3942..e98ad71 100644</span><br><span>--- a/src/northbridge/intel/pineview/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>@@ -118,7 +118,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span>diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>index 43442f1..c76e4be 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>@@ -57,7 +57,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span>diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>index 1009372..6c05efd 100644</span><br><span>--- a/src/northbridge/intel/x4x/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>@@ -116,7 +116,7 @@</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26574">change 26574</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 </div>
<div style="display:none"> Gerrit-Change-Number: 26574 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>