<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26583">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/broadwe: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/broadwell/acpi.c<br>M src/soc/intel/broadwell/chip.c<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/broadwell/ehci.c<br>M src/soc/intel/broadwell/include/soc/ramstage.h<br>M src/soc/intel/broadwell/lpc.c<br>M src/soc/intel/broadwell/me.c<br>M src/soc/intel/broadwell/pcie.c<br>M src/soc/intel/broadwell/sata.c<br>M src/soc/intel/broadwell/smbus.c<br>M src/soc/intel/broadwell/smmrelocate.c<br>M src/soc/intel/broadwell/systemagent.c<br>12 files changed, 65 insertions(+), 65 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/26583/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c</span><br><span>index 162542f..36d3e58 100644</span><br><span>--- a/src/soc/intel/broadwell/acpi.c</span><br><span>+++ b/src/soc/intel/broadwell/acpi.c</span><br><span>@@ -387,7 +387,7 @@</span><br><span> </span><br><span> static void generate_C_state_entries(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span> config_t *config = dev->chip_info;</span><br><span> acpi_cstate_t map[3];</span><br><span> int *set;</span><br><span>@@ -534,7 +534,7 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void generate_cpu_entries(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void generate_cpu_entries(struct device *device)</span><br><span> {</span><br><span> int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;</span><br><span> int totalcores = dev_count_cpu();</span><br><span>diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c</span><br><span>index ae3248a..70afa0d 100644</span><br><span>--- a/src/soc/intel/broadwell/chip.c</span><br><span>+++ b/src/soc/intel/broadwell/chip.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include <soc/ramstage.h></span><br><span> #include <soc/intel/broadwell/chip.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span> assign_resources(dev->link_list);</span><br><span> }</span><br><span>@@ -42,7 +42,7 @@</span><br><span> .init = &broadwell_init_cpus,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void broadwell_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void broadwell_enable(struct device *dev)</span><br><span> {</span><br><span> /* Set the operations if it is a special bus type */</span><br><span> if (dev->path.type == DEVICE_PATH_DOMAIN) {</span><br><span>@@ -64,7 +64,7 @@</span><br><span> .init = &broadwell_init_pre_device,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_set_subsystem(device_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span> unsigned int device)</span><br><span> {</span><br><span> if (!vendor || !device)</span><br><span>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c</span><br><span>index ecb7247..ee1fd52 100644</span><br><span>--- a/src/soc/intel/broadwell/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/cpu.c</span><br><span>@@ -197,7 +197,7 @@</span><br><span> </span><br><span> static void initialize_vr_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span> config_t *conf = dev->chip_info;</span><br><span> msr_t msr;</span><br><span> </span><br><span>@@ -452,7 +452,7 @@</span><br><span> </span><br><span> static void configure_thermal_target(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span> config_t *conf = dev->chip_info;</span><br><span> msr_t msr;</span><br><span> </span><br><span>@@ -572,7 +572,7 @@</span><br><span> }</span><br><span> </span><br><span> /* All CPUs including BSP will run the following function. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_core_init(device_t cpu)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_core_init(struct device *cpu)</span><br><span> {</span><br><span> /* Clear out pending MCEs */</span><br><span> configure_mca();</span><br><span>@@ -672,7 +672,7 @@</span><br><span> .post_mp_init = post_mp_init,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void broadwell_init_cpus(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void broadwell_init_cpus(struct device *dev)</span><br><span> {</span><br><span> struct bus *cpu_bus = dev->link_list;</span><br><span> </span><br><span>diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c</span><br><span>index e00fa25..b1ead77 100644</span><br><span>--- a/src/soc/intel/broadwell/ehci.c</span><br><span>+++ b/src/soc/intel/broadwell/ehci.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #include <soc/ehci.h></span><br><span> #include <soc/pch.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span> unsigned int device)</span><br><span> {</span><br><span> u8 access_cntl;</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h</span><br><span>index 1009bba..7292bcf 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/ramstage.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/ramstage.h</span><br><span>@@ -20,8 +20,8 @@</span><br><span> #include <soc/intel/broadwell/chip.h></span><br><span> </span><br><span> void broadwell_init_pre_device(void *chip_info);</span><br><span style="color: hsl(0, 100%, 40%);">-void broadwell_init_cpus(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void broadwell_pch_enable_dev(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void broadwell_init_cpus(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void broadwell_pch_enable_dev(struct device *dev);</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)</span><br><span> void broadwell_run_reference_code(void);</span><br><span>diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c</span><br><span>index 8e7f4de..c59326a 100644</span><br><span>--- a/src/soc/intel/broadwell/lpc.c</span><br><span>+++ b/src/soc/intel/broadwell/lpc.c</span><br><span>@@ -102,9 +102,9 @@</span><br><span> * 0x80 - The PIRQ is not routed.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *irq_dev;</span><br><span> config_t *config = dev->chip_info;</span><br><span> </span><br><span> pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);</span><br><span>@@ -147,7 +147,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span> {</span><br><span> u16 reg16;</span><br><span> const char *state;</span><br><span>@@ -362,7 +362,7 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_cg_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_cg_init(struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> u16 reg16;</span><br><span>@@ -460,7 +460,7 @@</span><br><span> pch_set_acpi_mode();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span> u32 reg;</span><br><span> struct resource *res;</span><br><span>@@ -522,7 +522,7 @@</span><br><span> * Note: this function assumes there is no overlap with the default LPC device's</span><br><span> * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -535,7 +535,7 @@</span><br><span> res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)</span><br><span> {</span><br><span> /*</span><br><span> * Check if the register is enabled. If so and the base exceeds the</span><br><span>@@ -548,7 +548,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_io_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_io_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> config_t *config = dev->chip_info;</span><br><span>@@ -573,7 +573,7 @@</span><br><span> pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span> global_nvs_t *gnvs;</span><br><span> </span><br><span>@@ -592,7 +592,7 @@</span><br><span> memset(gnvs, 0, sizeof(global_nvs_t));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southcluster_inject_dsdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southcluster_inject_dsdt(struct device *device)</span><br><span> {</span><br><span> global_nvs_t *gnvs;</span><br><span> </span><br><span>@@ -616,7 +616,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned long broadwell_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long broadwell_write_acpi_tables(struct device *device,</span><br><span> unsigned long current,</span><br><span> struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c</span><br><span>index ed2f728..ae0f48f 100644</span><br><span>--- a/src/soc/intel/broadwell/me.c</span><br><span>+++ b/src/soc/intel/broadwell/me.c</span><br><span>@@ -110,7 +110,7 @@</span><br><span> mei_dump(ptr, dword, offset, "WRITE");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span> u32 dword = pci_read_config32(dev, offset);</span><br><span> memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -433,7 +433,7 @@</span><br><span> * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read</span><br><span> * state machine on the BIOS end doesn't match the ME's state machine.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_mbp_give_up(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_mbp_give_up(struct device *dev)</span><br><span> {</span><br><span> struct mei_csr csr;</span><br><span> </span><br><span>@@ -449,7 +449,7 @@</span><br><span> * mbp clear routine. This will wait for the ME to indicate that</span><br><span> * the MBP has been read and cleared.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_mbp_clear(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_mbp_clear(struct device *dev)</span><br><span> {</span><br><span> int count;</span><br><span> struct me_hfs2 hfs2;</span><br><span>@@ -611,7 +611,7 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_finalize(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_finalize(struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span>@@ -653,7 +653,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span> struct me_hfs hfs;</span><br><span>@@ -723,7 +723,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct mei_csr host;</span><br><span>@@ -753,7 +753,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span> struct me_heres status;</span><br><span> u32 extend[8] = {0};</span><br><span>@@ -839,7 +839,7 @@</span><br><span> * Return 0 to indicate success (send LOCK+EOP)</span><br><span> * Return 1 to indicate success (send LOCK+EOP with NOACK)</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)</span><br><span> {</span><br><span> mbp_header mbp_hdr;</span><br><span> u32 me2host_pending;</span><br><span>@@ -968,7 +968,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span> config_t *config = dev->chip_info;</span><br><span> me_bios_path path = intel_me_path(dev);</span><br><span>@@ -1045,7 +1045,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_enable(struct device *dev)</span><br><span> {</span><br><span> /* Avoid talking to the device in S3 path */</span><br><span> if (acpi_is_wakeup_s3()) {</span><br><span>diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c</span><br><span>index 724f263..3fd5ea4 100644</span><br><span>--- a/src/soc/intel/broadwell/pcie.c</span><br><span>+++ b/src/soc/intel/broadwell/pcie.c</span><br><span>@@ -48,23 +48,23 @@</span><br><span> int coalesce;</span><br><span> int gbe_port;</span><br><span> int num_ports;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t ports[NUM_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *ports[NUM_ROOT_PORTS];</span><br><span> };</span><br><span> </span><br><span> static struct root_port_config rpc;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_is_first(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_is_first(struct device *dev)</span><br><span> {</span><br><span> return PCI_FUNC(dev->path.pci.devfn) == 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_is_last(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_is_last(struct device *dev)</span><br><span> {</span><br><span> return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);</span><br><span> }</span><br><span> </span><br><span> /* Root ports are numbered 1..N in the documentation. */</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_number(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_number(struct device *dev)</span><br><span> {</span><br><span> return PCI_FUNC(dev->path.pci.devfn) + 1;</span><br><span> }</span><br><span>@@ -94,7 +94,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_iosf_port_grant_count(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_iosf_port_grant_count(struct device *dev)</span><br><span> {</span><br><span> u8 update_val;</span><br><span> u32 rpcd = (pci_read_config32(dev, 0xfc) >> 14) & 0x3;</span><br><span>@@ -115,7 +115,7 @@</span><br><span> RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_init_config(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_init_config(struct device *dev)</span><br><span> {</span><br><span> int rp;</span><br><span> u32 data = 0;</span><br><span>@@ -186,7 +186,7 @@</span><br><span> /* Update devicetree with new Root Port function number assignment */</span><br><span> static void pch_pcie_device_set_func(int index, int pci_func)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> unsigned int new_devfn;</span><br><span> </span><br><span> dev = rpc.ports[index];</span><br><span>@@ -216,7 +216,7 @@</span><br><span> int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);</span><br><span> </span><br><span> for (i = 0; i < rpc.num_ports; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> int rp;</span><br><span> </span><br><span> dev = rpc.ports[i];</span><br><span>@@ -294,7 +294,7 @@</span><br><span> pcie_enable_clock_gating();</span><br><span> </span><br><span> for (i = 0; i < rpc.num_ports; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> u32 reg32;</span><br><span> int n = 0;</span><br><span> </span><br><span>@@ -359,7 +359,7 @@</span><br><span> RCBA32(RPFN) = rpc.new_rpfn;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_mark_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_mark_disable(struct device *dev)</span><br><span> {</span><br><span> /* Mark device as disabled. */</span><br><span> dev->enabled = 0;</span><br><span>@@ -367,7 +367,7 @@</span><br><span> rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_check_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_check_disable(struct device *dev)</span><br><span> {</span><br><span> int rp;</span><br><span> </span><br><span>@@ -629,7 +629,7 @@</span><br><span> pci_write_config16(dev, 0x1e, reg16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(struct device *dev)</span><br><span> {</span><br><span> /* Add this device to the root port config structure. */</span><br><span> root_port_init_config(dev);</span><br><span>@@ -649,7 +649,7 @@</span><br><span> root_port_commit_config();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_set_subsystem(device_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span> unsigned int device)</span><br><span> {</span><br><span> /* NOTE: This is not the default position! */</span><br><span>@@ -659,7 +659,7 @@</span><br><span> pci_write_config32(dev, 0x94, (device << 16) | vendor);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)</span><br><span> {</span><br><span> /* Set max snoop and non-snoop latency for Broadwell */</span><br><span> pci_write_config32(dev, off, 0x10031003);</span><br><span>diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c</span><br><span>index 7b9bd0c..3dadccc 100644</span><br><span>--- a/src/soc/intel/broadwell/sata.c</span><br><span>+++ b/src/soc/intel/broadwell/sata.c</span><br><span>@@ -267,7 +267,7 @@</span><br><span> * Set SATA controller mode early so the resource allocator can</span><br><span> * properly assign IO/Memory resources for the controller.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span> /* Get the chip configuration */</span><br><span> config_t *config = dev->chip_info;</span><br><span>diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c</span><br><span>index 1b21f30..0e0eb8b 100644</span><br><span>--- a/src/soc/intel/broadwell/smbus.c</span><br><span>+++ b/src/soc/intel/broadwell/smbus.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> #include <soc/ramstage.h></span><br><span> #include <soc/smbus.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_smbus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_smbus_init(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> u16 reg16;</span><br><span>@@ -43,7 +43,7 @@</span><br><span> outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span> u16 device;</span><br><span> struct resource *res;</span><br><span>@@ -56,7 +56,7 @@</span><br><span> return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)</span><br><span> {</span><br><span> u16 device;</span><br><span> struct resource *res;</span><br><span>@@ -73,7 +73,7 @@</span><br><span> .write_byte = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span> res->base = SMBUS_BASE_ADDRESS;</span><br><span>diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c</span><br><span>index 1ddf37a..2d90ebc 100644</span><br><span>--- a/src/soc/intel/broadwell/smmrelocate.c</span><br><span>+++ b/src/soc/intel/broadwell/smmrelocate.c</span><br><span>@@ -179,7 +179,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 northbridge_get_base_reg(device_t dev, int reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 northbridge_get_base_reg(struct device *dev, int reg)</span><br><span> {</span><br><span> u32 value;</span><br><span> </span><br><span>@@ -189,7 +189,7 @@</span><br><span> return value;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void fill_in_relocation_params(device_t dev,</span><br><span style="color: hsl(120, 100%, 40%);">+static void fill_in_relocation_params(struct device *dev,</span><br><span> struct smm_relocation_params *params)</span><br><span> {</span><br><span> u32 tseg_size;</span><br><span>@@ -270,7 +270,7 @@</span><br><span> void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span> size_t *smm_save_state_size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Setting up SMI for CPU\n");</span><br><span> </span><br><span>diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c</span><br><span>index d9dbfe9..14defaf 100644</span><br><span>--- a/src/soc/intel/broadwell/systemagent.c</span><br><span>+++ b/src/soc/intel/broadwell/systemagent.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)</span><br><span> {</span><br><span> u32 pciexbar_reg;</span><br><span> </span><br><span>@@ -70,7 +70,7 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)</span><br><span> {</span><br><span> u32 bar;</span><br><span> </span><br><span>@@ -89,7 +89,7 @@</span><br><span> /* There are special BARs that actually are programmed in the MCHBAR. These</span><br><span> * Intel special features, but they do consume resources that need to be</span><br><span> * accounted for. */</span><br><span style="color: hsl(0, 100%, 40%);">-static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,</span><br><span> u32 *len)</span><br><span> {</span><br><span> u32 bar;</span><br><span>@@ -109,7 +109,7 @@</span><br><span> struct fixed_mmio_descriptor {</span><br><span> unsigned int index;</span><br><span> u32 size;</span><br><span style="color: hsl(0, 100%, 40%);">- int (*get_resource)(device_t dev, unsigned int index,</span><br><span style="color: hsl(120, 100%, 40%);">+ int (*get_resource)(struct device *dev, unsigned int index,</span><br><span> u32 *base, u32 *size);</span><br><span> const char *description;</span><br><span> };</span><br><span>@@ -127,7 +127,7 @@</span><br><span> * Add all known fixed MMIO ranges that hang off the host bridge/memory</span><br><span> * controller device.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_add_fixed_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_add_fixed_mmio_resources(struct device *dev)</span><br><span> {</span><br><span> int i;</span><br><span> </span><br><span>@@ -184,7 +184,7 @@</span><br><span> const char *description;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void read_map_entry(device_t dev, struct map_entry *entry,</span><br><span style="color: hsl(120, 100%, 40%);">+static void read_map_entry(struct device *dev, struct map_entry *entry,</span><br><span> uint64_t *result)</span><br><span> {</span><br><span> uint64_t value;</span><br><span>@@ -253,14 +253,14 @@</span><br><span> [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_read_map_entries(device_t dev, uint64_t *values)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_read_map_entries(struct device *dev, uint64_t *values)</span><br><span> {</span><br><span> int i;</span><br><span> for (i = 0; i < NUM_MAP_ENTRIES; i++)</span><br><span> read_map_entry(dev, &memory_map[i], &values[i]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_report_map_entries(device_t dev, uint64_t *values)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_report_map_entries(struct device *dev, uint64_t *values)</span><br><span> {</span><br><span> int i;</span><br><span> for (i = 0; i < NUM_MAP_ENTRIES; i++) {</span><br><span>@@ -271,7 +271,7 @@</span><br><span> printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_add_dram_resources(device_t dev, int *resource_cnt)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_add_dram_resources(struct device *dev, int *resource_cnt)</span><br><span> {</span><br><span> unsigned long base_k, size_k;</span><br><span> unsigned long touud_k;</span><br><span>@@ -377,7 +377,7 @@</span><br><span> *resource_cnt = index;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void systemagent_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void systemagent_read_resources(struct device *dev)</span><br><span> {</span><br><span> int index = 0;</span><br><span> const bool vtd_capable =</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26583">change 26583</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26583"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff </div>
<div style="display:none"> Gerrit-Change-Number: 26583 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>