<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26565">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Fix a few things in set_enhanced_mode<br><br>Some things were coding errors, other things need to be fsb specific.<br><br>Most things here don't seem to matter all that much but better to get<br>it right.<br><br>Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/raminit_ddr23.c<br>1 file changed, 44 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/26565/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>index 6bf356f..da5f76e 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>@@ -1814,6 +1814,7 @@</span><br><span> static void set_enhanced_mode(struct sysinfo *s)</span><br><span> {</span><br><span> u8 ch, reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span> </span><br><span> MCHBAR32(0xfb0) = 0x1000d024;</span><br><span> MCHBAR32(0xfb4) = 0xc842;</span><br><span>@@ -1824,7 +1825,7 @@</span><br><span> if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz)</span><br><span> MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2;</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12f) = MCHBAR8(0x12f) & 0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x12f) = MCHBAR8(0x12f) & ~0x2;</span><br><span> MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0;</span><br><span> MCHBAR32(0xfa8) = 0x30d400;</span><br><span> </span><br><span>@@ -1842,15 +1843,48 @@</span><br><span> </span><br><span> reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | 0x219100c2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2c) = 0x44a53;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz</span><br><span style="color: hsl(120, 100%, 40%);">+ ? 0x20000 : 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = 0x219100c2;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~0x10000;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~0x10000;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = 0x44a00;</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (s->selected_timings.fsb_clk) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case FSB_CLOCK_1333MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= 0x62;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case FSB_CLOCK_1066MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= 0x5a;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ case FSB_CLOCK_800MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= 0x53;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x2c) = reg32;</span><br><span> MCHBAR32(0x30) = 0x1f5a86;</span><br><span> MCHBAR32(0x34) = 0x1902810;</span><br><span> MCHBAR32(0x38) = 0xf7000000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x3c) = 0x23014410;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | 0x8f038000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x20) = 0x33001;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = 0x23014410;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.fsb_clk > FSB_CLOCK_800MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = (reg32 & ~0x2000000) | 0x44000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3c) = reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = 0x8f038000;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~0x4000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = 0x00013001;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= 0x20000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x20) = reg32;</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1);</span><br><span> }</span><br><span> </span><br><span>@@ -1919,7 +1953,7 @@</span><br><span> MCHBAR32(0x14) = 0x0010691f;</span><br><span> MCHBAR32(0x18) = 0xdf6437f7;</span><br><span> MCHBAR32(0x1c) = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x30000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x60000000;</span><br><span> MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000;</span><br><span> MCHBAR16(0x115) = (u16) reg1;</span><br><span> MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2;</span><br><span>@@ -1942,8 +1976,8 @@</span><br><span> MCHBAR32(0x300) = 0xc0b0a08;</span><br><span> MCHBAR32(0x304) = 0x6040201;</span><br><span> MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x610) = 0x232;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x612) = 0x2864;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16(0x610) = reg3;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16(0x612) = reg4;</span><br><span> MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000;</span><br><span> MCHBAR32(0xae4) = 0;</span><br><span> MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26565">change 26565</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26565"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd </div>
<div style="display:none"> Gerrit-Change-Number: 26565 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>