<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26564">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Select stacked mode under some circumstances<br><br>It looks like this hardware has a bug where the display controller<br>does not work properly when dram is clocked 533MHz and the channels<br>are configured in non-stacked mode.<br><br>Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/raminit.c<br>1 file changed, 21 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/26564/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c</span><br><span>index 9e649b0..016fbd9 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit.c</span><br><span>@@ -352,6 +352,26 @@</span><br><span>   }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* With DDR3 and 533MHz mem clock and a gfx device enabled the display</span><br><span style="color: hsl(120, 100%, 40%);">+ * is not usable in stacked mode, so select stacked mode accordingly */</span><br><span style="color: hsl(120, 100%, 40%);">+static void select_stacked_mode(struct sysinfo *s)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+    u32 deven;</span><br><span style="color: hsl(120, 100%, 40%);">+    /* Only a problem on DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+  if (s->spd_type == DDR2)</span><br><span style="color: hsl(120, 100%, 40%);">+           return;</span><br><span style="color: hsl(120, 100%, 40%);">+       /* Does not matter if only one channel is populated */</span><br><span style="color: hsl(120, 100%, 40%);">+        if (!CHANNEL_IS_POPULATED(s->dimms, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+                     || !CHANNEL_IS_POPULATED(s->dimms, 1))</span><br><span style="color: hsl(120, 100%, 40%);">+             return;</span><br><span style="color: hsl(120, 100%, 40%);">+       if (s->selected_timings.mem_clk != MEM_CLOCK_533MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+               return;</span><br><span style="color: hsl(120, 100%, 40%);">+       /* IGD0EN gets disabled if not present  before this code runs */</span><br><span style="color: hsl(120, 100%, 40%);">+      deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN);</span><br><span style="color: hsl(120, 100%, 40%);">+      if (deven & IGD0EN)</span><br><span style="color: hsl(120, 100%, 40%);">+               s->stacked_mode = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,</span><br><span>              struct abs_timings *saved_timings, struct sysinfo *s)</span><br><span> {</span><br><span>@@ -544,6 +564,7 @@</span><br><span>     else</span><br><span>                 select_cas_dramfreq_ddr3(s, &saved_timings);</span><br><span>     select_discrete_timings(s, &saved_timings);</span><br><span style="color: hsl(120, 100%, 40%);">+       select_stacked_mode(s);</span><br><span> }</span><br><span> </span><br><span> static void find_dimm_config(struct sysinfo *s)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26564">change 26564</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26564"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021 </div>
<div style="display:none"> Gerrit-Change-Number: 26564 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>