<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26529">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/via/vx900: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I31143e1c7f1c52dec9673f75d73031632049ddbf<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/via/vx900/chrome9hd.c<br>M src/northbridge/via/vx900/lpc.c<br>M src/northbridge/via/vx900/northbridge.c<br>M src/northbridge/via/vx900/pcie.c<br>M src/northbridge/via/vx900/sata.c<br>M src/northbridge/via/vx900/traf_ctrl.c<br>6 files changed, 41 insertions(+), 41 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/26529/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c</span><br><span>index 00b5c4b..fb5841e 100644</span><br><span>--- a/src/northbridge/via/vx900/chrome9hd.c</span><br><span>+++ b/src/northbridge/via/vx900/chrome9hd.c</span><br><span>@@ -98,7 +98,7 @@</span><br><span> u8 vx900_int15_get_5f18_bl(void)</span><br><span> {</span><br><span>        u8 reg8, ret;</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  /*</span><br><span>    * BL Bit[7:4]</span><br><span>        * Memory Data Rate (not to be confused with fCLK)</span><br><span>@@ -137,7 +137,7 @@</span><br><span>     vga_sr_write(0x37, device & 0xff);  /*  SID low  byte */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void chrome9hd_handle_uma(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void chrome9hd_handle_uma(struct device *dev)</span><br><span> {</span><br><span>       u8 fb_pow = vx900_get_chrome9hd_fb_pow();</span><br><span> </span><br><span>@@ -165,11 +165,11 @@</span><br><span>  *</span><br><span>  * This document is only available under NDA.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void chrome9hd_biosguide_init_seq(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void chrome9hd_biosguide_init_seq(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span>                                     PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-     device_t host = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *host = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span>                                     PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);</span><br><span> </span><br><span>     /* Step 1 - Enable VGA controller */</span><br><span>@@ -208,7 +208,7 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void chrome9hd_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void chrome9hd_init(struct device *dev)</span><br><span> {</span><br><span>         printk(BIOS_DEBUG, "======================================================\n");</span><br><span>    printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");</span><br><span>@@ -243,17 +243,17 @@</span><br><span>        dump_pci_device(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void chrome9hd_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void chrome9hd_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span>                                     PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);</span><br><span>  /* FIXME: here? -=- ACLK 250MHz */</span><br><span>   pci_mod_config8(mcu, 0xbb, 0, 0x01);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void chrome9hd_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void chrome9hd_disable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span>                                     PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);</span><br><span>  /* Disable GFX - This step effectively renders the GFX inert</span><br><span>          * It won't even show up as a PCI device during enumeration */</span><br><span>diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c</span><br><span>index 43e4d4c..075a872 100644</span><br><span>--- a/src/northbridge/via/vx900/lpc.c</span><br><span>+++ b/src/northbridge/via/vx900/lpc.c</span><br><span>@@ -47,7 +47,7 @@</span><br><span>  * it will work, but perhaps this should be more configurable.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_misc_stuff(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_misc_stuff(struct device *dev)</span><br><span> {</span><br><span>        char extint;</span><br><span>         u8 val;</span><br><span>@@ -71,7 +71,7 @@</span><br><span>  }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_dma_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_dma_setup(struct device *dev)</span><br><span> {</span><br><span>    /* These are the steps recommended by VIA in order to get DMA running */</span><br><span> </span><br><span>@@ -104,12 +104,12 @@</span><br><span>  * We are assuming this is called before the drivers/generic/ioapic code,</span><br><span>  * which should be the case if devicetree.cb is set up properly.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_ioapic_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_ioapic_setup(struct device *dev)</span><br><span> {</span><br><span>    /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb</span><br><span>          * If it's not, then the generic ioapic driver will not set it up</span><br><span>         * correctly, and the MP table will not be correctly generated */</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t ioapic;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *ioapic;</span><br><span>       for (ioapic = dev->next; ioapic; ioapic = ioapic->next) {</span><br><span>              if (ioapic->path.type == DEVICE_PATH_IOAPIC)</span><br><span>                      break;</span><br><span>@@ -151,7 +151,7 @@</span><br><span>         pci_mod_config8(dev, 0x58, 0, 1 << 6);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_interrupt_stuff(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_interrupt_stuff(struct device *dev)</span><br><span> {</span><br><span>     /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports</span><br><span>         * And enable I/O recovery time */</span><br><span>@@ -177,14 +177,14 @@</span><br><span>   vx900_lpc_ioapic_setup(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_init(struct device *dev)</span><br><span> {</span><br><span>   vx900_lpc_interrupt_stuff(dev);</span><br><span>      vx900_lpc_misc_stuff(dev);</span><br><span>   dump_pci_device(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>      struct resource *res;</span><br><span>        pci_dev_read_resources(dev);</span><br><span>@@ -206,7 +206,7 @@</span><br><span>   res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_lpc_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_lpc_set_resources(struct device *dev)</span><br><span> {</span><br><span>         struct resource *mmio, *spi;</span><br><span>         u32 reg;</span><br><span>@@ -248,7 +248,7 @@</span><br><span> #if IS_ENABLED(CONFIG_PIRQ_ROUTE)</span><br><span> void pirq_assign_irqs(const u8 * pirq)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t lpc;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *lpc;</span><br><span> </span><br><span>      lpc = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span>                           PCI_DEVICE_ID_VIA_VX900_LPC, 0);</span><br><span>diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c</span><br><span>index 3f839c7..8f23e88 100644</span><br><span>--- a/src/northbridge/via/vx900/northbridge.c</span><br><span>+++ b/src/northbridge/via/vx900/northbridge.c</span><br><span>@@ -57,7 +57,7 @@</span><br><span>  return uma_memory_base;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u64 vx900_get_top_of_ram(device_t mcu)</span><br><span style="color: hsl(120, 100%, 40%);">+static u64 vx900_get_top_of_ram(struct device *mcu)</span><br><span> {</span><br><span>      u16 reg16;</span><br><span>   /* The last valid DRAM address is computed by the MCU</span><br><span>@@ -94,7 +94,7 @@</span><br><span>  *</span><br><span>  * @return The new top of memory.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)</span><br><span style="color: hsl(120, 100%, 40%);">+static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm)</span><br><span> {</span><br><span>       size_t i;</span><br><span>    u8 reg8, start8, end8, start, end;</span><br><span>@@ -214,7 +214,7 @@</span><br><span>     return newtor;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_set_resources(struct device *dev)</span><br><span> {</span><br><span>       u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;</span><br><span> </span><br><span>@@ -226,7 +226,7 @@</span><br><span>              "========================================\n");</span><br><span> </span><br><span>     int idx = 10;</span><br><span style="color: hsl(0, 100%, 40%);">-   const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *const *mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span>                                            PCI_DEVICE_ID_VIA_VX900_MEMCTRL,</span><br><span>                                             0);</span><br><span>     if (!mcu) {</span><br><span>@@ -283,7 +283,7 @@</span><br><span>    assign_resources(dev->link_list);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_read_resources(struct device *dev)</span><br><span> {</span><br><span>       /* Our fixed resources start at 0 */</span><br><span>         int idx = 0;</span><br><span>@@ -310,7 +310,7 @@</span><br><span>   .scan_bus = pci_domain_scan_bus,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_init(struct device *dev)</span><br><span> {</span><br><span>  initialize_cpus(dev->link_list);</span><br><span> }</span><br><span>@@ -323,7 +323,7 @@</span><br><span>       .scan_bus = 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span>        /* Set the operations if it is a special bus type */</span><br><span>         if (dev->path.type == DEVICE_PATH_DOMAIN) {</span><br><span>diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c</span><br><span>index ae81739..1d3ecd9 100644</span><br><span>--- a/src/northbridge/via/vx900/pcie.c</span><br><span>+++ b/src/northbridge/via/vx900/pcie.c</span><br><span>@@ -35,7 +35,7 @@</span><br><span>  * If the link never comes up, we hang.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_pcie_link_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_pcie_link_init(struct device *dev)</span><br><span> {</span><br><span>       u8 reg8;</span><br><span>     u32 reg32;</span><br><span>@@ -81,12 +81,12 @@</span><br><span>      * time? */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_pex_dev_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_pex_dev_set_resources(struct device *dev)</span><br><span> {</span><br><span>  assign_resources(dev->link_list);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_pex_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_pex_init(struct device *dev)</span><br><span> {</span><br><span>   /* FIXME: For some reason, PEX0 hangs on init. Find issue, fix it. */</span><br><span>        if ((dev->path.pci.devfn & 0x7) == 0)</span><br><span>diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c</span><br><span>index e0a54bd..4df0053 100644</span><br><span>--- a/src/northbridge/via/vx900/sata.c</span><br><span>+++ b/src/northbridge/via/vx900/sata.c</span><br><span>@@ -71,7 +71,7 @@</span><br><span>                printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_dbg_sata_errors(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_dbg_sata_errors(struct device *dev)</span><br><span> {</span><br><span>       /* Port 0 */</span><br><span>         if (pci_read_config8(dev, 0xa0) & (1 << 0)) {</span><br><span>@@ -100,7 +100,7 @@</span><br><span>        0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 sata_phy_read32(device_t dev, u8 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 sata_phy_read32(struct device *dev, u8 index)</span><br><span> {</span><br><span>   /* The SATA PHY control registers are accessed by a funny index/value</span><br><span>         * scheme. Each byte (0,1,2,3) has its own 4-bit index */</span><br><span>@@ -112,7 +112,7 @@</span><br><span>      return pci_read_config32(dev, 0x64);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_phy_write32(device_t dev, u8 index, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_phy_write32(struct device *dev, u8 index, u32 val)</span><br><span> {</span><br><span>         /* The SATA PHY control registers are accessed by a funny index/value</span><br><span>         * scheme. Each byte (0,1,2,3) has its own 4-bit index */</span><br><span>@@ -124,7 +124,7 @@</span><br><span>      pci_write_config32(dev, 0x64, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg)</span><br><span> {</span><br><span>  size_t i;</span><br><span>    u32 *data = (u32 *) cfg;</span><br><span>@@ -133,7 +133,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg)</span><br><span> {</span><br><span>  size_t i;</span><br><span>    u32 *data = (u32 *) cfg;</span><br><span>@@ -175,7 +175,7 @@</span><br><span>  * Our only option is to operate in IDE mode. We choose native IDE so that we</span><br><span>  * can freely assign an IRQ, and are not forced to use IRQ14</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_native_ide_mode(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_native_ide_mode(struct device *dev)</span><br><span> {</span><br><span>    /* Disable subclass write protect */</span><br><span>         pci_mod_config8(dev, 0x45, 1 << 7, 0);</span><br><span>@@ -187,7 +187,7 @@</span><br><span>   pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_sata_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_sata_init(struct device *dev)</span><br><span> {</span><br><span>        /* Enable SATA primary channel IO access */</span><br><span>  pci_mod_config8(dev, 0x40, 0, 1 << 1);</span><br><span>@@ -255,7 +255,7 @@</span><br><span>   vx900_dbg_sata_errors(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_sata_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_sata_read_resources(struct device *dev)</span><br><span> {</span><br><span>      pci_dev_read_resources(dev);</span><br><span> }</span><br><span>diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c</span><br><span>index 0fb55b3..8bdf25c 100644</span><br><span>--- a/src/northbridge/via/vx900/traf_ctrl.c</span><br><span>+++ b/src/northbridge/via/vx900/traf_ctrl.c</span><br><span>@@ -45,10 +45,10 @@</span><br><span>  * We are assuming this is called before the drivers/generic/ioapic code,</span><br><span>  * which should be the case if devicetree.cb is set up properly.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_north_ioapic_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_north_ioapic_setup(struct device *dev)</span><br><span> {</span><br><span>    u8 base_val;</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t ioapic;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *ioapic;</span><br><span>       ioapic_config_t *config;</span><br><span>     /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb</span><br><span>          * If it's not, then the generic ioapic driver will not set it up</span><br><span>@@ -103,7 +103,7 @@</span><br><span>  *</span><br><span>  * FIXME: triple-quadruple-check this</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_pex_link_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_pex_link_setup(struct device *dev)</span><br><span> {</span><br><span>   u8 reg8;</span><br><span>     struct northbridge_via_vx900_config *nb = (void *)dev->chip_info;</span><br><span>@@ -120,7 +120,7 @@</span><br><span>   pci_write_config8(dev, 0xb0, reg8);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_traf_ctr_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_traf_ctr_init(struct device *dev)</span><br><span> {</span><br><span>  vx900_north_ioapic_setup(dev);</span><br><span>       vx900_pex_link_setup(dev);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26529">change 26529</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26529"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I31143e1c7f1c52dec9673f75d73031632049ddbf </div>
<div style="display:none"> Gerrit-Change-Number: 26529 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>