<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26530">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6x: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I05f23504148d934109814b8f3c1c2a334366496a<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/bd82x6x/azalia.c<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/bd82x6x/pci.c<br>M src/southbridge/intel/bd82x6x/pcie.c<br>M src/southbridge/intel/bd82x6x/sata.c<br>M src/southbridge/intel/bd82x6x/smbus.c<br>M src/southbridge/intel/bd82x6x/usb_ehci.c<br>M src/southbridge/intel/bd82x6x/usb_xhci.c<br>M src/southbridge/intel/bd82x6x/watchdog.c<br>9 files changed, 29 insertions(+), 29 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26530/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>index 02165d6..d3d57aa 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>@@ -337,7 +337,7 @@</span><br><span>  return "HDEF";</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>       if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index ea7a808..8e9b827 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -107,9 +107,9 @@</span><br><span>  * 0x80 - The PIRQ is not routed.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *irq_dev;</span><br><span>      /* Interrupt 11 is not used by legacy devices and so can always be used for</span><br><span>     PCI interrupts. Full legacy IRQ routing is complicated and hard to</span><br><span>           get right. Fortunately all modern OS use MSI and so it's not that big of</span><br><span>@@ -144,7 +144,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_gpi_routing(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_gpi_routing(struct device *dev)</span><br><span> {</span><br><span>    /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -173,7 +173,7 @@</span><br><span>  pci_write_config32(dev, GPIO_ROUT, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span> {</span><br><span>       u8 reg8;</span><br><span>     u16 reg16, pmbase;</span><br><span>@@ -396,7 +396,7 @@</span><br><span>     RCBA32(HPTC) = reg32;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_clock_gating(struct device *dev)</span><br><span> {</span><br><span>        u32 reg32;</span><br><span>   u16 reg16;</span><br><span>@@ -561,7 +561,7 @@</span><br><span>     pch_spi_init(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>     struct resource *res;</span><br><span>        config_t *config = dev->chip_info;</span><br><span>@@ -625,13 +625,13 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span>  pch_decode_init(dev);</span><br><span>        return pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable(struct device *dev)</span><br><span> {</span><br><span>  /* Enable PCH Display Port */</span><br><span>        RCBA16(DISPBDF) = 0x0010;</span><br><span>@@ -640,7 +640,7 @@</span><br><span>      pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -651,7 +651,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span>    global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));</span><br><span> </span><br><span>@@ -684,7 +684,7 @@</span><br><span> </span><br><span> void acpi_fill_fadt(acpi_fadt_t *fadt)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span>    config_t *chip = dev->chip_info;</span><br><span>  u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;</span><br><span>      int c2_latency;</span><br><span>@@ -819,9 +819,9 @@</span><br><span>        return "LPCB";</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_fill_ssdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_fill_ssdt(struct device *device)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span>    config_t *chip = dev->chip_info;</span><br><span> </span><br><span>      intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c</span><br><span>index 85e431e..f86d8a01e 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pci.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pci.c</span><br><span>@@ -100,7 +100,7 @@</span><br><span>    ich_pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   /* NOTE: This is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>index 1f4c157..1e87838 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>@@ -265,13 +265,13 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(struct device *dev)</span><br><span> {</span><br><span>    /* Power Management init before enumeration */</span><br><span>       pch_pcie_pm_early(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pciexp_scan_bridge(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pciexp_scan_bridge(struct device *dev)</span><br><span> {</span><br><span>        struct southbridge_intel_bd82x6x_config *config = dev->chip_info;</span><br><span> </span><br><span>@@ -306,7 +306,7 @@</span><br><span>       return NULL;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>       /* NOTE: This is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c</span><br><span>index d4268da..78c5964 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/sata.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/sata.c</span><br><span>@@ -208,7 +208,7 @@</span><br><span>         pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span>         /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -233,7 +233,7 @@</span><br><span>  pci_write_config16(dev, 0x90, map);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -249,7 +249,7 @@</span><br><span>       return "SATA";</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_fill_ssdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_fill_ssdt(struct device *dev)</span><br><span> {</span><br><span>       config_t *config = dev->chip_info;</span><br><span>        generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c</span><br><span>index 33908905..e8eec4c 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/smbus.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/smbus.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_smbus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_smbus_init(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res;</span><br><span>        u16 reg16;</span><br><span>@@ -41,7 +41,7 @@</span><br><span>               outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>         u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -54,7 +54,7 @@</span><br><span>    return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span>  u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -72,7 +72,7 @@</span><br><span>    .write_byte     = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -87,7 +87,7 @@</span><br><span>         .set_subsystem    = smbus_set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_read_resources(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span>        res->base = SMBUS_IO_BASE;</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>index b5ce820..4822ec5 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span>       printk(BIOS_DEBUG, "done.\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   u8 access_cntl;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c</span><br><span>index 6acc63b..9c9d8b5 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/usb_xhci.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c</span><br><span>@@ -56,7 +56,7 @@</span><br><span>         return "XHC";</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void xhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void xhci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c</span><br><span>index 74f69b0..9a867e4 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/watchdog.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/watchdog.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span>   //</span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  unsigned long value, base;</span><br><span> </span><br><span>       /* Turn off the ICH7 watchdog. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26530">change 26530</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26530"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I05f23504148d934109814b8f3c1c2a334366496a </div>
<div style="display:none"> Gerrit-Change-Number: 26530 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>