<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26543">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation: Add HP Compaq 8200 and NPCD378<br><br>Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M Documentation/index.md<br>A Documentation/mainboard/hp/compaq_8200_sff.md<br>A Documentation/mainboard/hp/compaq_8200_sff_flash1.jpg<br>A Documentation/mainboard/hp/compaq_8200_sff_flash2.jpg<br>M Documentation/mainboard/index.md<br>A Documentation/superio/index.md<br>A Documentation/superio/nuvoton/npcd378.md<br>7 files changed, 295 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/26543/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/index.md b/Documentation/index.md</span><br><span>index 69fb7f5..a3cda52 100644</span><br><span>--- a/Documentation/index.md</span><br><span>+++ b/Documentation/index.md</span><br><span>@@ -20,3 +20,4 @@</span><br><span> * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)</span><br><span> * [Sandy Bridge Raminit](Intel/NativeRaminit/Sandybridge.md)</span><br><span> * [Mainboard-specific documentation](mainboard/index.md)</span><br><span style="color: hsl(120, 100%, 40%);">+* [SuperIO-specific documentation](superio/index.md)</span><br><span>diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md</span><br><span>new file mode 100644</span><br><span>index 0000000..6052920</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/hp/compaq_8200_sff.md</span><br><span>@@ -0,0 +1,158 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# HP Compaq 8200 Elite SFF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop</span><br><span style="color: hsl(120, 100%, 40%);">+from [HP].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## TODO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The following things are still missing from this coreboot port:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- Extended HWM reporting</span><br><span style="color: hsl(120, 100%, 40%);">+- Advanced LED control</span><br><span style="color: hsl(120, 100%, 40%);">+- Powerconfiguration in S3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Run `make menuconfig` and select _HP_/_Compaq 8200 Elite SFF_ in the _Mainboard_</span><br><span style="color: hsl(120, 100%, 40%);">+menu.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Flashing coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The Compaq 8200 Elite SFF has an 8 MiB SPI flash, that can be programmed from within</span><br><span style="color: hsl(120, 100%, 40%);">+Linux running on the board, or directly with an SPI programmer.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Internal programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The SPI flash can be accessed using [flashrom].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### External programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+External programming with an SPI adapter and [flashrom] does work, but it powers the</span><br><span style="color: hsl(120, 100%, 40%);">+whole southbridge complex. You need to supply enough current through the programming adapter.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,</span><br><span style="color: hsl(120, 100%, 40%);">+as otherwise there's not enough space near the flash.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Position of SOIC-8 flash IC near 2nd DIMM holder**</span><br><span style="color: hsl(120, 100%, 40%);">+![][compaq_8200_flash1]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Closeup view of SOIC-8 flash IC**</span><br><span style="color: hsl(120, 100%, 40%);">+![][compaq_8200_flash2]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Technology</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Northbridge | sandybridge |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Southbridge | bd82x6x |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CPU | model_206ax |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SuperIO | :doc:`../../superio/nuvoton/npcd378` |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| EC | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Coprocessor | Intel ME |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Mainboard components</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Vendor</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### CPU</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+-----------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Value |</span><br><span style="color: hsl(120, 100%, 40%);">++=====================+===================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| Socketed CPU | Yes |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+-----------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Model | Core i Series 2nd/3rd Generation |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+-----------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### DRAM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-------------------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Value |</span><br><span style="color: hsl(120, 100%, 40%);">++===============================+============+</span><br><span style="color: hsl(120, 100%, 40%);">+| Number of DRAM DIMMs | 4 |</span><br><span style="color: hsl(120, 100%, 40%);">++-------------------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Max supported DDR speed (Mhz) | 800 |</span><br><span style="color: hsl(120, 100%, 40%);">++-------------------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Flash</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Value |</span><br><span style="color: hsl(120, 100%, 40%);">++=====================+============+</span><br><span style="color: hsl(120, 100%, 40%);">+| Socketed flash | no |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Model | MX25L6406E |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Size | 8 MiB |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| In circuit flashing | yes |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Internal flashing | yes |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Internal slots</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++----------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Count |</span><br><span style="color: hsl(120, 100%, 40%);">++================+========+</span><br><span style="color: hsl(120, 100%, 40%);">+| PCIe x16 Gen3 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++----------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PCIe x4 Gen2 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++----------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PCI | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++----------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SATA Gen3 | 4 |</span><br><span style="color: hsl(120, 100%, 40%);">++----------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Ports</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Count |</span><br><span style="color: hsl(120, 100%, 40%);">++==================+========+</span><br><span style="color: hsl(120, 100%, 40%);">+| PS/2 | 2 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DSUB-9 serial | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DSUB-25 LPT | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| VGA | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Displayport | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Audio | 3 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| USB Gen2 | 10 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Gigabit Ethernet | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+:doc:`../../superio/nuvoton/npcd378`</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707</span><br><span style="color: hsl(120, 100%, 40%);">+[HP]: https://www.hp.com/</span><br><span style="color: hsl(120, 100%, 40%);">+[flashrom]: https://flashrom.org/Flashrom</span><br><span>diff --git a/Documentation/mainboard/hp/compaq_8200_sff_flash1.jpg b/Documentation/mainboard/hp/compaq_8200_sff_flash1.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..67aeedf</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/hp/compaq_8200_sff_flash1.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/mainboard/hp/compaq_8200_sff_flash2.jpg b/Documentation/mainboard/hp/compaq_8200_sff_flash2.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..c406d98</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/hp/compaq_8200_sff_flash2.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index b62ad67..23e1ed2 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -5,3 +5,7 @@</span><br><span> ## SiFive</span><br><span> </span><br><span> - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## HP</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)</span><br><span>diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md</span><br><span>new file mode 100644</span><br><span>index 0000000..eef4d57</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/superio/index.md</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# SuperIO-specific documentation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This section contains documentation about coreboot on specific SuperIOs.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Nuvoton</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [NPCD378](nuvoton/npcd378.md)</span><br><span>diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md</span><br><span>new file mode 100644</span><br><span>index 0000000..54023d9</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/superio/nuvoton/npcd378.md</span><br><span>@@ -0,0 +1,125 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# NPCD378</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This page describes the [Nuvoton] SuperIO chip that can be found on various [HP]</span><br><span style="color: hsl(120, 100%, 40%);">+mainboards.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+As no Datasheet is available most of the functions have been reverse engineered and</span><br><span style="color: hsl(120, 100%, 40%);">+might be inacurate or wrong.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## LDNs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| LDN # | Function |</span><br><span style="color: hsl(120, 100%, 40%);">++=======+===========================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | FDC |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | Parallel Port |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | Com1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 3 | Com2 / IR |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 4 | LED and PWR button CTRL |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 5 | PS/2 AUX |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6 | PS/2 KB |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 7 | WDT1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8 | HWM |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0xf | GPIO |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0x15 | I2C ? |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0x1e | SUSPEND CTL ? |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0x1c | GPIO ? |</span><br><span style="color: hsl(120, 100%, 40%);">++-------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Follows [Nuvoton]'s default FDC register set. See [NCT6102D] for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Follows [Nuvoton]'s default LPT register set. See [NCT6102D] for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Follows [Nuvoton]'s default COM1 register set. See [NCT6102D] for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Follows [Nuvoton]'s default COM2 register set. See [NCT6102D] for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+On most SuperIOs the use of LDN4 is forbidden. That's not the case on NPCD378.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle</span><br><span style="color: hsl(120, 100%, 40%);">+and power button behaviour on normal / during S3 resume.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+A custom PS/2 AUX port.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Follows [Nuvoton]'s default KBC register set. See [NCT6102D] for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Looks like a WDT.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### LDN8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Custom HWM space. It exposes 256 byte of IO config space.</span><br><span style="color: hsl(120, 100%, 40%);">+See [HWM](#HWM) for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## HWM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Register</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The registers are accessible via IO space and are located at LDN8's IOBASE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| IOBASE offset | Register |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0x4 | Host Write CTRL |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0x10 - 0xfe | HWM Page # |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0xff | Page index select |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Host Write CTRL</span><br><span style="color: hsl(120, 100%, 40%);">+Bit 0 must be cleared prior to writing any of the HWM register and it must be</span><br><span style="color: hsl(120, 100%, 40%);">+set after writing to HWM register to signal the SuperIO that data has changed.</span><br><span style="color: hsl(120, 100%, 40%);">+Reading register is possible at any time and doesn't need special locking.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### HWM Page</span><br><span style="color: hsl(120, 100%, 40%);">+The SuperIO exposes 16 different pages. Nearly all registers are unknown.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Page 1**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| IOBASE offset | Register |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0x98 | PSU fan PWM |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+-----------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Page index</span><br><span style="color: hsl(120, 100%, 40%);">+The 4 LSB of the page index register selects which HWM page is active.</span><br><span style="color: hsl(120, 100%, 40%);">+A write takes effect immediately.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[NCT6102D]: https://www.nuvoton.com/resource-files/NCT6102D_NCT6106D_Datasheet_V1_0.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+[Nuvoton]: http://www.nuvoton.com/hq/</span><br><span style="color: hsl(120, 100%, 40%);">+[HP]: https://www.hp.com/</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26543">change 26543</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212 </div>
<div style="display:none"> Gerrit-Change-Number: 26543 </div>
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<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>