<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26458">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/cpu.c<br>M src/soc/amd/stoneyridge/include/soc/acpi.h<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/lpc.c<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/sm.c<br>8 files changed, 39 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/26458/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c</span><br><span>index 02ee6fa..735990f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi.c</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi.c</span><br><span>@@ -233,11 +233,11 @@</span><br><span> header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void generate_cpu_entries(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void generate_cpu_entries(struct device *device)</span><br><span> {</span><br><span> int cores, cpu, plen = 6;</span><br><span> u32 pcontrol_blk = ACPI_GPE0_BLK;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t cdb_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *cdb_dev;</span><br><span> </span><br><span> /* Stoney Ridge is single node, just report # of cores */</span><br><span> cdb_dev = dev_find_slot(0, NB_DEVFN);</span><br><span>@@ -258,7 +258,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southbridge_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span> unsigned long current,</span><br><span> struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>@@ -286,7 +286,7 @@</span><br><span> gnvs->pcnt = dev_count_cpu();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_inject_dsdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_inject_dsdt(struct device *device)</span><br><span> {</span><br><span> struct global_nvs_t *gnvs;</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index 46dcfa8..3b73a05 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -107,7 +107,7 @@</span><br><span> .acpi_name = soc_acpi_name,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span> /* Set the operations if it is a special bus type */</span><br><span> if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c</span><br><span>index 2c415a3..4dd371c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/cpu.c</span><br><span>+++ b/src/soc/amd/stoneyridge/cpu.c</span><br><span>@@ -55,7 +55,7 @@</span><br><span> </span><br><span> static int get_cpu_count(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t nb = dev_find_slot(0, HT_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *nb = dev_find_slot(0, HT_DEVFN);</span><br><span> return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1;</span><br><span> }</span><br><span> </span><br><span>@@ -115,7 +115,7 @@</span><br><span> mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void model_15_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void model_15_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Model 15 Init.\n");</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h</span><br><span>index 69ab599..3212ec7 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/acpi.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h</span><br><span>@@ -30,10 +30,10 @@</span><br><span> #define FADT_PM_PROFILE PM_UNSPECIFIED</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southbridge_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span> unsigned long current, struct acpi_rsdp *rsdp);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_inject_dsdt(device_t device);</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_inject_dsdt(struct device *device);</span><br><span> </span><br><span> const char *soc_acpi_name(const struct device *dev);</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 365a9f5..666be10 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -107,9 +107,9 @@</span><br><span> * 0 on success, < 0 on failure.</span><br><span> */</span><br><span> int smm_subregion(int sub, void **start, size_t *size);</span><br><span style="color: hsl(0, 100%, 40%);">-void domain_enable_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void domain_read_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void domain_set_resources(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void domain_enable_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void domain_read_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void domain_set_resources(struct device *dev);</span><br><span> void fam15_finalize(void *chip_info);</span><br><span> void setup_uma_memory(void);</span><br><span> uint32_t nb_ioapic_read(unsigned int index);</span><br><span>diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c</span><br><span>index eb51281..4bf5a4f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/lpc.c</span><br><span>+++ b/src/soc/amd/stoneyridge/lpc.c</span><br><span>@@ -34,11 +34,11 @@</span><br><span> #include <soc/southbridge.h></span><br><span> #include <soc/nvs.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_init(struct device *dev)</span><br><span> {</span><br><span> u8 byte;</span><br><span> u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *sm_dev;</span><br><span> </span><br><span> /*</span><br><span> * Enable the LPC Controller</span><br><span>@@ -108,7 +108,7 @@</span><br><span> pm_write8(PM_SERIRQ_CONF, byte);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> global_nvs_t *gnvs;</span><br><span>@@ -165,7 +165,7 @@</span><br><span> pci_dev_set_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_child_resource(device_t child,</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_child_resource(struct device *child,</span><br><span> u32 *reg,</span><br><span> u32 *reg_x)</span><br><span> {</span><br><span>@@ -299,7 +299,7 @@</span><br><span> * @param dev the device whose children's resources are to be enabled</span><br><span> *</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_enable_childrens_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_enable_childrens_resources(struct device *dev)</span><br><span> {</span><br><span> struct bus *link;</span><br><span> u32 reg, reg_x;</span><br><span>@@ -308,7 +308,7 @@</span><br><span> reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);</span><br><span> </span><br><span> for (link = dev->link_list; link; link = link->next) {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *child;</span><br><span> for (child = link->children; child;</span><br><span> child = child->sibling) {</span><br><span> if (child->enabled</span><br><span>@@ -323,7 +323,7 @@</span><br><span> pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span> pci_dev_enable_resources(dev);</span><br><span> lpc_enable_childrens_resources(dev);</span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index 2cefb91..6af1351 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -41,11 +41,11 @@</span><br><span> #include <stdlib.h></span><br><span> #include <string.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,</span><br><span> u32 io_min, u32 io_max)</span><br><span> {</span><br><span> u32 tempreg;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span> </span><br><span> /* io range allocation. Limit */</span><br><span> tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)</span><br><span>@@ -59,7 +59,7 @@</span><br><span> u32 mmio_min, u32 mmio_max)</span><br><span> {</span><br><span> u32 tempreg;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span> </span><br><span> /* io range allocation. Limit */</span><br><span> tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);</span><br><span>@@ -68,7 +68,7 @@</span><br><span> pci_write_config32(addr_map, reg, tempreg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -86,7 +86,7 @@</span><br><span> res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_resource(device_t dev, struct resource *resource, u32 nodeid)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)</span><br><span> {</span><br><span> resource_t rbase, rend;</span><br><span> unsigned int reg, link_num;</span><br><span>@@ -135,7 +135,7 @@</span><br><span> * but it is too difficult to deal with the resource allocation magic.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void create_vga_resource(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void create_vga_resource(struct device *dev)</span><br><span> {</span><br><span> struct bus *link;</span><br><span> </span><br><span>@@ -154,7 +154,7 @@</span><br><span> pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_resources(struct device *dev)</span><br><span> {</span><br><span> struct bus *bus;</span><br><span> struct resource *res;</span><br><span>@@ -197,7 +197,7 @@</span><br><span> return (unsigned long)current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void northbridge_fill_ssdt_generator(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void northbridge_fill_ssdt_generator(struct device *device)</span><br><span> {</span><br><span> msr_t msr;</span><br><span> char pscope[] = "\\_SB.PCI0";</span><br><span>@@ -218,7 +218,7 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned long agesa_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long agesa_write_acpi_tables(struct device *device,</span><br><span> unsigned long current,</span><br><span> acpi_rsdp_t *rsdp)</span><br><span> {</span><br><span>@@ -355,7 +355,7 @@</span><br><span> </span><br><span> void fam15_finalize(void *chip_info)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> u32 value;</span><br><span> dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */</span><br><span> pci_write_config32(dev, 0xf8, 0);</span><br><span>@@ -368,10 +368,10 @@</span><br><span> pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void domain_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void domain_read_resources(struct device *dev)</span><br><span> {</span><br><span> unsigned int reg;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span> </span><br><span> /* Find the already assigned resource pairs */</span><br><span> for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {</span><br><span>@@ -381,7 +381,7 @@</span><br><span> /* Is this register allocated? */</span><br><span> if ((base & 3) != 0) {</span><br><span> unsigned int nodeid, reg_link;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t reg_dev = dev_find_slot(0, HT_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *reg_dev = dev_find_slot(0, HT_DEVFN);</span><br><span> if (reg < 0xc0) /* mmio */</span><br><span> nodeid = (limit & 0xf) + (base & 0x30);</span><br><span> else /* io */</span><br><span>@@ -405,14 +405,14 @@</span><br><span> pci_domain_read_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void domain_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void domain_enable_resources(struct device *dev)</span><br><span> {</span><br><span> /* Must be called after PCI enumeration and resource allocation */</span><br><span> if (!romstage_handoff_is_resume())</span><br><span> do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void domain_set_resources(struct device *dev)</span><br><span> {</span><br><span> uint64_t uma_base = get_uma_base();</span><br><span> uint32_t uma_size = get_uma_size();</span><br><span>diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c</span><br><span>index d4f428f3..278f8a8 100644</span><br><span>--- a/src/soc/amd/stoneyridge/sm.c</span><br><span>+++ b/src/soc/amd/stoneyridge/sm.c</span><br><span>@@ -32,12 +32,12 @@</span><br><span> * The southbridge enables SATA by default in SMBUS Control.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sm_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sm_init(struct device *dev)</span><br><span> {</span><br><span> setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_recv_byte(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_recv_byte(struct device *dev)</span><br><span> {</span><br><span> u8 device;</span><br><span> struct resource *res;</span><br><span>@@ -51,7 +51,7 @@</span><br><span> return do_smbus_recv_byte(res->base, device);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_send_byte(device_t dev, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_send_byte(struct device *dev, u8 val)</span><br><span> {</span><br><span> u8 device;</span><br><span> struct resource *res;</span><br><span>@@ -65,7 +65,7 @@</span><br><span> return do_smbus_send_byte(res->base, device, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span> u8 device;</span><br><span> struct resource *res;</span><br><span>@@ -79,7 +79,7 @@</span><br><span> return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span> u8 device;</span><br><span> struct resource *res;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26458">change 26458</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26458"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2 </div>
<div style="display:none"> Gerrit-Change-Number: 26458 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>