<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26460">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: No space after defined<br><br>Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/ec/lenovo/h8/acpi/thermal.asl<br>M src/mainboard/google/rambi/romstage.c<br>M src/soc/broadcom/cygnus/ddr_init.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/fsp_bd82x6x/pch.h<br>M src/southbridge/intel/fsp_i89xx/pch.h<br>M src/southbridge/intel/fsp_rangeley/soc.h<br>M src/southbridge/intel/ibexpeak/pch.h<br>M src/southbridge/intel/lynxpoint/pch.h<br>9 files changed, 13 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/26460/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl</span><br><span>index aaced60..86fc311 100644</span><br><span>--- a/src/ec/lenovo/h8/acpi/thermal.asl</span><br><span>+++ b/src/ec/lenovo/h8/acpi/thermal.asl</span><br><span>@@ -15,7 +15,7 @@</span><br><span> </span><br><span> Scope(\_TZ)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (EC_LENOVO_H8_ME_WORKAROUND)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(EC_LENOVO_H8_ME_WORKAROUND)</span><br><span>     Name (MEB1, 0)</span><br><span>       Name (MEB2, 0)</span><br><span> #endif</span><br><span>@@ -85,7 +85,7 @@</span><br><span>                 }</span><br><span> </span><br><span>                Method(_TMP) {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (EC_LENOVO_H8_ME_WORKAROUND)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(EC_LENOVO_H8_ME_WORKAROUND)</span><br><span>                      /* Avoid tripping alarm if ME isn't booted at all yet */</span><br><span>                         If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) {</span><br><span>                              Return (C2K(40))</span><br><span>@@ -172,7 +172,7 @@</span><br><span>               }</span><br><span> </span><br><span>                Method(_TMP) {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (EC_LENOVO_H8_ME_WORKAROUND)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(EC_LENOVO_H8_ME_WORKAROUND)</span><br><span>                      /* Avoid tripping alarm if ME isn't booted at all yet */</span><br><span>                         If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) {</span><br><span>                              Return (C2K(40))</span><br><span>diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c</span><br><span>index 25fe859..005ddc3 100644</span><br><span>--- a/src/mainboard/google/rambi/romstage.c</span><br><span>+++ b/src/mainboard/google/rambi/romstage.c</span><br><span>@@ -35,7 +35,7 @@</span><br><span> #ifdef GPIO_SSUS_40_PAD_USE_PULLDOWN</span><br><span>        /* To prevent floating pin on shipped systems. */</span><br><span>    ssus_enable_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K);</span><br><span style="color: hsl(0, 100%, 40%);">-#elif defined (GPIO_SSUS_40_PAD)</span><br><span style="color: hsl(120, 100%, 40%);">+#elif defined(GPIO_SSUS_40_PAD)</span><br><span>    ssus_disable_internal_pull(GPIO_SSUS_40_PAD);</span><br><span> #endif</span><br><span>      ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);</span><br><span>diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>index 1a5fd86..c208457 100644</span><br><span>--- a/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>+++ b/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>@@ -713,7 +713,7 @@</span><br><span>   return ret;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#elif defined (CONFIG_SPI_FLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_IS_IN_SPI_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+#elif defined(CONFIG_SPI_FLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_IS_IN_SPI_FLASH</span><br><span> </span><br><span> static int write_shmoo_to_flash(void *buf, int length)</span><br><span> {</span><br><span>@@ -761,7 +761,7 @@</span><br><span>     return ret;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#elif defined (CONFIG_ENV_IS_IN_FLASH)</span><br><span style="color: hsl(120, 100%, 40%);">+#elif defined(CONFIG_ENV_IS_IN_FLASH)</span><br><span> </span><br><span> static int write_shmoo_to_flash(void *buf, int length)</span><br><span> {</span><br><span>@@ -841,7 +841,7 @@</span><br><span>   /* Read SHMOO data from NAND */</span><br><span>      flptr = (volatile uint32_t *)(IPROC_NAND_MEM_BASE + CONFIG_SHMOO_REUSE_NAND_OFFSET);</span><br><span>         offset = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / SHMOO_MIN_BLOCK_SIZE * SHMOO_MIN_BLOCK_SIZE;</span><br><span style="color: hsl(0, 100%, 40%);">-#elif defined (CONFIG_ENV_IS_IN_FLASH)</span><br><span style="color: hsl(120, 100%, 40%);">+#elif defined(CONFIG_ENV_IS_IN_FLASH)</span><br><span>     /* Read SHMOO data from NOR */</span><br><span>       flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + CONFIG_SHMOO_REUSE_NOR_OFFSET);</span><br><span>   offset = 0;</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index ebcb058..d7656b3 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -54,7 +54,7 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_pch_finalize_smm(void);</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>index 5b42271..1f1c18a 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>@@ -55,7 +55,7 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_pch_finalize_smm(void);</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h</span><br><span>index 4471788..a1d2a4b 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/pch.h</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/pch.h</span><br><span>@@ -54,7 +54,7 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_pch_finalize_smm(void);</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>index eaf9556..0917201 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>@@ -50,7 +50,7 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_soc_finalize_smm(void);</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index f9583e0..4e86c82 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -49,7 +49,7 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_pch_finalize_smm(void);</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>index f14a339..70f2834 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>@@ -91,7 +91,7 @@</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_pch_finalize_smm(void);</span><br><span> void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ);</span><br><span> void usb_ehci_disable(device_t dev);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26460">change 26460</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.corebo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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 </div>
<div style="display:none"> Gerrit-Change-Number: 26460 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>