<p>Raul Rangel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26478">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge: Move agesa out of bootblock<br><br>This is Garrett's patch with a bit of cleanup.<br><br>BUG=b:65442212<br>TEST=Was able to boot, suspend and resume on grunt.<br><br>Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7<br>Signed-off-by: Raul E Rangel <rrangel@chromium.org><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/romstage.c<br>2 files changed, 44 insertions(+), 57 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/26478/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index 6ee2095..52a10c6 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -52,27 +52,6 @@</span><br><span> set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * To move AGESA calls to romstage, just move agesa_call() and bsp_agesa_call()</span><br><span style="color: hsl(0, 100%, 40%);">- * to romstage.c. Also move the call to bsp_agesa_call() to the marked location</span><br><span style="color: hsl(0, 100%, 40%);">- * in romstage.c.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void agesa_call(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x37);</span><br><span style="color: hsl(0, 100%, 40%);">- do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38);</span><br><span style="color: hsl(0, 100%, 40%);">- /* APs will not exit amdinitearly */</span><br><span style="color: hsl(0, 100%, 40%);">- do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void bsp_agesa_call(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */</span><br><span style="color: hsl(0, 100%, 40%);">- agesa_call();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span> {</span><br><span> amd_initmmio();</span><br><span>@@ -97,37 +76,6 @@</span><br><span> post_code(0x90);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This step is in bootblock because the SMU FW1 must be loaded prior to</span><br><span style="color: hsl(0, 100%, 40%);">- * issuing any reset to the system. Set up just enough to get the command</span><br><span style="color: hsl(0, 100%, 40%);">- * to the PSP. A side effect of placing this step here is we will always</span><br><span style="color: hsl(0, 100%, 40%);">- * load a RO version of FW1 and never a RW version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * todo: If AMD develops a more robust methodology, move this function to</span><br><span style="color: hsl(0, 100%, 40%);">- * romstage.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void load_smu_fw1(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 base, limit, cmd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Open a posted hole from 0x80000000 : 0xfed00000-1 */</span><br><span style="color: hsl(0, 100%, 40%);">- base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;</span><br><span style="color: hsl(0, 100%, 40%);">- limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Preload a value into "BAR3" and enable it */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable memory access and master */</span><br><span style="color: hsl(0, 100%, 40%);">- cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void bootblock_soc_init(void)</span><br><span> {</span><br><span> if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))</span><br><span>@@ -137,11 +85,6 @@</span><br><span> u32 val = cpuid_eax(1);</span><br><span> printk(BIOS_DEBUG, "Family_Model: %08x\n", val);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))</span><br><span style="color: hsl(0, 100%, 40%);">- load_smu_fw1();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- bsp_agesa_call();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Initialize any early i2c buses. */</span><br><span> i2c_soc_early_init();</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 0e019f7..03d23af 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -40,6 +40,44 @@</span><br><span> /* By default, don't do anything */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void load_smu_fw1(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 base, limit, cmd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Open a posted hole from 0x80000000 : 0xfed00000-1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;</span><br><span style="color: hsl(120, 100%, 40%);">+ limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Preload a value into "BAR3" and enable it */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable memory access and master */</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void agesa_call(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x37);</span><br><span style="color: hsl(120, 100%, 40%);">+ do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x38);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* APs will not exit amdinitearly */</span><br><span style="color: hsl(120, 100%, 40%);">+ do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void bsp_agesa_call(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */</span><br><span style="color: hsl(120, 100%, 40%);">+ agesa_call();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span> struct postcar_frame pcf;</span><br><span>@@ -60,6 +98,12 @@</span><br><span> </span><br><span> console_init();</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))</span><br><span style="color: hsl(120, 100%, 40%);">+ load_smu_fw1();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bsp_agesa_call();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> mainboard_romstage_entry(s3_resume);</span><br><span> </span><br><span> if (!s3_resume) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26478">change 26478</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 </div>
<div style="display:none"> Gerrit-Change-Number: 26478 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Raul Rangel <rrangel@chromium.org> </div>