<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26423">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/via/cn700: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: Ic58bb58b88ffc309472ee9ffc8a9c8619659811b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/via/cn700/agp.c<br>M src/northbridge/via/cn700/northbridge.c<br>M src/northbridge/via/cn700/northbridge.h<br>M src/northbridge/via/cn700/vga.c<br>4 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/26423/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c</span><br><span>index 55e5fe3..d035573 100644</span><br><span>--- a/src/northbridge/via/cn700/agp.c</span><br><span>+++ b/src/northbridge/via/cn700/agp.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #include "cn700.h"</span><br><span> </span><br><span> /* This is the main AGP device, and only one used when configured for AGP 2.0 */</span><br><span style="color: hsl(0, 100%, 40%);">-static void agp_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void agp_init(struct device *dev)</span><br><span> {</span><br><span>    u32 reg32;</span><br><span> </span><br><span>@@ -117,7 +117,7 @@</span><br><span>  * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the</span><br><span>  * config in this device takes presidence. We configure both just to be safe.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void agp_bridge_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void agp_bridge_init(struct device *dev)</span><br><span> {</span><br><span>     printk(BIOS_DEBUG, "Setting up AGP bridge device\n");</span><br><span> </span><br><span>@@ -152,7 +152,7 @@</span><br><span>    pci_write_config8(dev, 0x45, 0x72);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void agp_bridge_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void agp_bridge_read_resources(struct device *dev)</span><br><span> {</span><br><span>      struct resource *resource;</span><br><span> </span><br><span>diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c</span><br><span>index f745a0e..78bb6f9 100644</span><br><span>--- a/src/northbridge/via/cn700/northbridge.c</span><br><span>+++ b/src/northbridge/via/cn700/northbridge.c</span><br><span>@@ -30,9 +30,9 @@</span><br><span> #include "northbridge.h"</span><br><span> #include "cn700.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void memctrl_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void memctrl_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t vlink_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *vlink_dev;</span><br><span>    u16 reg16;</span><br><span>   u8 ranks, pagec, paged, pagee, pagef, shadowreg;</span><br><span> </span><br><span>@@ -93,11 +93,11 @@</span><br><span>   .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span>        /* The order is important to find the correct RAM size. */</span><br><span>   static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };</span><br><span style="color: hsl(0, 100%, 40%);">- device_t mc_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *mc_dev;</span><br><span>       u32 pci_tolm;</span><br><span> </span><br><span>    printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");</span><br><span>@@ -151,7 +151,7 @@</span><br><span>     .scan_bus         = pci_domain_scan_bus,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_init(struct device *dev)</span><br><span> {</span><br><span>  initialize_cpus(dev->link_list);</span><br><span> }</span><br><span>diff --git a/src/northbridge/via/cn700/northbridge.h b/src/northbridge/via/cn700/northbridge.h</span><br><span>index 5aaada9..1780b4d 100644</span><br><span>--- a/src/northbridge/via/cn700/northbridge.h</span><br><span>+++ b/src/northbridge/via/cn700/northbridge.h</span><br><span>@@ -17,6 +17,6 @@</span><br><span> #ifndef NORTHBRIDGE_VIA_CN700_H</span><br><span> #define NORTHBRIDGE_VIA_CN700_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-extern unsigned int cn700_scan_root_bus(device_t root, unsigned int max);</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned int cn700_scan_root_bus(struct device *root, unsigned int max);</span><br><span> </span><br><span> #endif /* NORTHBRIDGE_VIA_CN700_H */</span><br><span>diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c</span><br><span>index 4925f2b..493159a 100644</span><br><span>--- a/src/northbridge/via/cn700/vga.c</span><br><span>+++ b/src/northbridge/via/cn700/vga.c</span><br><span>@@ -72,7 +72,7 @@</span><br><span>   return res;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vga_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void vga_init(struct device *dev)</span><br><span> {</span><br><span>        u8 reg8;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26423">change 26423</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26423"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic58bb58b88ffc309472ee9ffc8a9c8619659811b </div>
<div style="display:none"> Gerrit-Change-Number: 26423 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>