<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26404">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge/amd/sr5650: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I91dfbba3c734218baf4f2de3cf88066d657096c1<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sr5650/cmn.h<br>M src/southbridge/amd/sr5650/ht.c<br>M src/southbridge/amd/sr5650/pcie.c<br>M src/southbridge/amd/sr5650/sr5650.c<br>M src/southbridge/amd/sr5650/sr5650.h<br>5 files changed, 92 insertions(+), 92 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/26404/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h</span><br><span>index 0c0fd29..869f34b 100644</span><br><span>--- a/src/southbridge/amd/sr5650/cmn.h</span><br><span>+++ b/src/southbridge/amd/sr5650/cmn.h</span><br><span>@@ -34,29 +34,29 @@</span><br><span> #define AB_INDX   0xCD8</span><br><span> #define AB_DATA   (AB_INDX+4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)</span><br><span> {</span><br><span>    pci_write_config32(dev, index_reg, index);</span><br><span>   return pci_read_config32(dev, index_reg + 0x4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index, u32 data)</span><br><span> {</span><br><span>  pci_write_config32(dev, index_reg, index);</span><br><span>   pci_write_config32(dev, index_reg + 0x4, data);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>  return nb_read_index((nb_dev), NBMISC_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>   nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,</span><br><span>                                    u32 val)</span><br><span> {</span><br><span>     u32 reg_old, reg;</span><br><span>@@ -68,27 +68,27 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 htiu_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 htiu_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>    return nb_read_index((nb_dev), NBHTIU_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>       nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 nbmc_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>   return nb_read_index((nb_dev), NBMC_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>         nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,</span><br><span>                                u32 val)</span><br><span> {</span><br><span>       u32 reg_old, reg;</span><br><span>@@ -100,7 +100,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,</span><br><span>                             u32 val)</span><br><span> {</span><br><span>      u32 reg_old, reg;</span><br><span>@@ -112,7 +112,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask,</span><br><span>                                     u8 val)</span><br><span> {</span><br><span>     u8 reg_old, reg;</span><br><span>@@ -124,7 +124,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,</span><br><span>                              u32 val)</span><br><span> {</span><br><span>       u32 reg_old, reg;</span><br><span>@@ -136,7 +136,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>    u32 reg_old, reg;</span><br><span>    reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);</span><br><span>diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c</span><br><span>index b79efc2..563c67d 100644</span><br><span>--- a/src/southbridge/amd/sr5650/ht.c</span><br><span>+++ b/src/southbridge/amd/sr5650/ht.c</span><br><span>@@ -177,8 +177,8 @@</span><br><span> </span><br><span>        if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {</span><br><span>           uint32_t reg;</span><br><span style="color: hsl(0, 100%, 40%);">-           device_t amd_ht_cfg_dev;</span><br><span style="color: hsl(0, 100%, 40%);">-                device_t amd_addr_map_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+            struct device *amd_ht_cfg_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+                struct device *amd_addr_map_dev;</span><br><span>             resource_t res_base;</span><br><span>                 resource_t res_end;</span><br><span>          uint32_t base;</span><br><span>diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c</span><br><span>index e198b87..9e2bd92 100644</span><br><span>--- a/src/southbridge/amd/sr5650/pcie.c</span><br><span>+++ b/src/southbridge/amd/sr5650/pcie.c</span><br><span>@@ -46,9 +46,9 @@</span><br><span>  0                       /* GppPwr */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ValidatePortEn(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+static void ValidatePortEn(struct device *nb_dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ValidatePortEn(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void ValidatePortEn(struct device *nb_dev)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span>@@ -56,7 +56,7 @@</span><br><span> * Compliant with CIM_33's PCIEPowerOffGppPorts</span><br><span> * Power off unused GPP lines</span><br><span> *****************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>  printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port);</span><br><span>      u32 reg;</span><br><span>@@ -124,7 +124,7 @@</span><br><span> </span><br><span> /**********************************************************************</span><br><span> **********************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void switching_gpp1_configurations(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void switching_gpp1_configurations(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span>    u32 reg;</span><br><span>     struct southbridge_amd_sr5650_config *cfg =</span><br><span>@@ -165,7 +165,7 @@</span><br><span> </span><br><span> /**********************************************************************</span><br><span> **********************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void switching_gpp2_configurations(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void switching_gpp2_configurations(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span>         u32 reg;</span><br><span>     struct southbridge_amd_sr5650_config *cfg =</span><br><span>@@ -203,7 +203,7 @@</span><br><span>    /* Follow the procedure for PCIE-GPP2 common initialization and</span><br><span>       * link training sequence. */</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void switching_gpp3a_configurations(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span>        u32 reg;</span><br><span>     struct southbridge_amd_sr5650_config *cfg =</span><br><span>@@ -263,7 +263,7 @@</span><br><span> * The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration</span><br><span> * Space to a 256MB range within the first 4GB of addressable memory.</span><br><span> *****************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void enable_pcie_bar3(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_pcie_bar3(struct device *nb_dev)</span><br><span> {</span><br><span>    printk(BIOS_DEBUG, "%s\n", __func__);</span><br><span>      set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);      /* Enables writes to the BAR3 register. */</span><br><span>@@ -279,7 +279,7 @@</span><br><span> * We should disable bar3 when we want to exit sr5650_enable, because bar3 will be</span><br><span> * remapped in set_resource later.</span><br><span> *****************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void disable_pcie_bar3(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void disable_pcie_bar3(struct device *nb_dev)</span><br><span> {</span><br><span>  printk(BIOS_DEBUG, "%s\n", __func__);</span><br><span>      pci_write_config32(nb_dev, 0x1C, 0);    /* clear BAR3 address */</span><br><span>@@ -290,7 +290,7 @@</span><br><span> /*</span><br><span>  * GEN2 Software Compliance</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-void init_gen2(device_t nb_dev, device_t dev, u8 port)</span><br><span style="color: hsl(120, 100%, 40%);">+void init_gen2(struct device *nb_dev, struct device *dev, u8 port)</span><br><span> {</span><br><span>    u32 reg, val;</span><br><span> </span><br><span>@@ -358,7 +358,7 @@</span><br><span>  * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP3a Ports</span><br><span>  * PcieLibCplBufferAllocation</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gpp3a_cpl_buf_alloc(struct device *nb_dev, struct device *dev)</span><br><span> {</span><br><span>       u8 dev_index;</span><br><span>        u8 *slave_cpl;</span><br><span>@@ -406,7 +406,7 @@</span><br><span>  * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports</span><br><span>  * PcieLibCplBufferAllocation</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gpp12_cpl_buf_alloc(struct device *nb_dev, struct device *dev)</span><br><span> {</span><br><span>         u8 gpp_cfg;</span><br><span>  u8 value;</span><br><span>@@ -442,14 +442,14 @@</span><br><span> /*</span><br><span>  * Enable LCLK clock gating</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void EnableLclkGating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void EnableLclkGating(struct device *dev)</span><br><span> {</span><br><span>       u8 port;</span><br><span>     u32 reg = 0;</span><br><span>         u32 mask = 0;</span><br><span>        u32 value = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t nb_dev = dev_find_slot(0, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t clk_f1= dev_find_slot(0, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *nb_dev = dev_find_slot(0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+  struct device *clk_f1= dev_find_slot(0, 1);</span><br><span> </span><br><span>      reg = 0xE8;</span><br><span>  port = dev->path.pci.devfn >> 3;</span><br><span>@@ -502,7 +502,7 @@</span><br><span> * port:</span><br><span> * p2p bridge number, 4-10</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>     uint8_t training_ok = 1;</span><br><span> </span><br><span>@@ -829,7 +829,7 @@</span><br><span>  * Step 21: Register Locking</span><br><span>  * Lock HWInit Register of each pcie core</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void lock_hwinitreg(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lock_hwinitreg(struct device *nb_dev)</span><br><span> {</span><br><span>    /* Step 21: Register Locking, Lock HWInit Register */</span><br><span>        set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);</span><br><span>@@ -844,7 +844,7 @@</span><br><span>  */</span><br><span> void sr56x0_lock_hwinitreg(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+  struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span> </span><br><span>       /* Lock HWInit Register */</span><br><span>   lock_hwinitreg(nb_dev);</span><br><span>@@ -859,7 +859,7 @@</span><br><span> /*****************************************</span><br><span> * Compliant with CIM_33's PCIEConfigureGPPCore</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void config_gpp_core(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void config_gpp_core(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span>       u32 reg;</span><br><span> </span><br><span>@@ -886,7 +886,7 @@</span><br><span> /*****************************************</span><br><span> * Compliant with CIM_33's PCIEMiscClkProg</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void pcie_config_misc_clk(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pcie_config_misc_clk(struct device *nb_dev)</span><br><span> {</span><br><span>     u32 reg;</span><br><span>     //struct bus pbus; /* fake bus for dev0 fun1 */</span><br><span>diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>index 47de24c..aca971e 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.c</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> extern void set_pcie_reset(void);</span><br><span> </span><br><span> struct resource * sr5650_retrieve_cpu_mmio_resource() {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t domain;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *domain;</span><br><span>       struct resource *res;</span><br><span> </span><br><span>    for (domain = all_devices; domain; domain = domain->next) {</span><br><span>@@ -51,7 +51,7 @@</span><br><span> }</span><br><span> </span><br><span> /* extension registers */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)</span><br><span> {</span><br><span>        /*get BAR3 base address for nbcfg0x1c */</span><br><span>     u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;</span><br><span>@@ -62,7 +62,7 @@</span><br><span>   return *((u32 *) addr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>      u32 reg_old, reg;</span><br><span> </span><br><span>@@ -81,42 +81,42 @@</span><br><span>  }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_p_read_index(device_t dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_p_read_index(struct device *dev, u32 index)</span><br><span> {</span><br><span>      return nb_read_index((dev), NBPCIE_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_p_write_index(device_t dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)</span><br><span> {</span><br><span>    nb_write_index((dev), NBPCIE_INDEX, (index), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>        return nb_read_index((nb_dev), NBPCIE_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>       nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index)</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index)</span><br><span> {</span><br><span>   return nb_read_index((nb_dev), L2CFG_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)</span><br><span style="color: hsl(120, 100%, 40%);">+void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)</span><br><span> {</span><br><span>      nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index)</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index)</span><br><span> {</span><br><span>         return nb_read_index((nb_dev), L1CFG_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)</span><br><span style="color: hsl(120, 100%, 40%);">+void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)</span><br><span> {</span><br><span>      nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data));</span><br><span> }</span><br><span>@@ -130,8 +130,8 @@</span><br><span> void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)</span><br><span> {</span><br><span>      /* K8 Function1 is address map */</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+        struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));</span><br><span style="color: hsl(120, 100%, 40%);">+  struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span> </span><br><span>     if (in_out) {</span><br><span>                u32 dword, sblk;</span><br><span>@@ -157,7 +157,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>      switch (port) {</span><br><span>      case 2:         /* GPP1, bit4-5 */</span><br><span>@@ -194,7 +194,7 @@</span><br><span> *   0: no device is present.</span><br><span> *   1: device is present and is trained.</span><br><span> ********************************************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>       u16 count = 5000;</span><br><span>    u32 lc_state, reg, current_link_width, lane_mask;</span><br><span>@@ -300,7 +300,7 @@</span><br><span> /*</span><br><span>  * Set Top Of Memory below and above 4G.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_set_tom(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_set_tom(struct device *nb_dev)</span><br><span> {</span><br><span>        msr_t sysmem;</span><br><span> </span><br><span>@@ -315,12 +315,12 @@</span><br><span>    htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 get_vid_did(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 get_vid_did(struct device *dev)</span><br><span> {</span><br><span>       return pci_read_config32(dev, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void detect_and_enable_iommu(device_t iommu_dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+void detect_and_enable_iommu(struct device *iommu_dev) {</span><br><span>       uint32_t dword;</span><br><span>      uint8_t l1_target;</span><br><span>   unsigned char iommu;</span><br><span>@@ -332,7 +332,7 @@</span><br><span>   if (iommu) {</span><br><span>                 printk(BIOS_DEBUG, "Initializing IOMMU\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-               device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+          struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span> </span><br><span>               if (!nb_dev) {</span><br><span>                       printk(BIOS_WARNING, "Unable to find SR5690 device!  IOMMU NOT initialized\n");</span><br><span>@@ -496,7 +496,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_read_resources(struct device *dev)</span><br><span> {</span><br><span>  unsigned char iommu;</span><br><span>         struct resource *res;</span><br><span>@@ -521,7 +521,7 @@</span><br><span>  compact_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_set_resources(struct device *dev)</span><br><span> {</span><br><span>      unsigned char iommu;</span><br><span>         struct resource *res;</span><br><span>@@ -549,12 +549,12 @@</span><br><span>        pci_dev_set_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_enable_resources(struct device *dev)</span><br><span> {</span><br><span>    detect_and_enable_iommu(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_nb_pci_table(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_nb_pci_table(struct device *nb_dev)</span><br><span> {   /* NBPOR_InitPOR function. */</span><br><span>        u8 temp8;</span><br><span>    u16 temp16;</span><br><span>@@ -609,9 +609,9 @@</span><br><span> * case 0 will be called twice, one is by CPU in hypertransport.c line458,</span><br><span> * the other is by sr5650.</span><br><span> ***********************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t nb_dev = 0, sb_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *nb_dev = 0, sb_dev = 0;</span><br><span>       int dev_ind;</span><br><span>         struct southbridge_amd_sr5650_config *cfg;</span><br><span> </span><br><span>@@ -823,14 +823,14 @@</span><br><span> {</span><br><span>  uint8_t *p;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+  struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span>   if (!nb_dev) {</span><br><span>               printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "</span><br><span>                            "device!  IVRS table not generated...\n");</span><br><span>                 return (unsigned long)ivrs;</span><br><span>  }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   device_t iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));</span><br><span>        if (!iommu_dev) {</span><br><span>            printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "</span><br><span>                            "IOMMU device!  IVRS table not generated...\n");</span><br><span>@@ -890,7 +890,7 @@</span><br><span>     return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southbridge_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span>                                             unsigned long current,</span><br><span>                                               struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h</span><br><span>index ea7005c..c63bc04 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.h</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.h</span><br><span>@@ -89,47 +89,47 @@</span><br><span> extern PCIE_CFG AtiPcieCfg;</span><br><span> </span><br><span> /* ----------------- export functions ----------------- */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_p_read_index(device_t dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_p_write_index(device_t dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index);</span><br><span style="color: hsl(0, 100%, 40%);">-void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data);</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index);</span><br><span style="color: hsl(0, 100%, 40%);">-void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);</span><br><span style="color: hsl(0, 100%, 40%);">-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_set_tom(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_p_read_index(struct device *dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_p_write_index(struct device *dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index);</span><br><span style="color: hsl(120, 100%, 40%);">+void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data);</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index);</span><br><span style="color: hsl(120, 100%, 40%);">+void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_set_tom(struct device *nb_dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current,</span><br><span>                                           struct acpi_rsdp *rsdp);</span><br><span> </span><br><span> void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);</span><br><span style="color: hsl(0, 100%, 40%);">-void enable_pcie_bar3(device_t nb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void disable_pcie_bar3(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_pcie_bar3(struct device *nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void disable_pcie_bar3(struct device *nb_dev);</span><br><span> </span><br><span> void enable_sr5650_dev8(void);</span><br><span> void sr5650_htinit(void);</span><br><span> void sr5650_htinit_dect_and_enable_isochronous_link(void);</span><br><span> void sr5650_early_setup(void);</span><br><span> void sr5650_before_pci_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_enable(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void config_gpp_core(device_t nb_dev, device_t sb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void pcie_config_misc_clk(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_enable(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_gfx_init(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void config_gpp_core(struct device *nb_dev, struct device *sb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void pcie_config_misc_clk(struct device *nb_dev);</span><br><span> void fam10_optimization(void);</span><br><span> void sr5650_disable_pcie_bridge(void);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 get_vid_did(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void detect_and_enable_iommu(device_t iommu_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_read_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_set_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_enable_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_nb_pci_table(device_t nb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void init_gen2(device_t nb_dev, device_t dev, u8 port);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 get_vid_did(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void detect_and_enable_iommu(struct device *iommu_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_read_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_set_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_enable_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_nb_pci_table(struct device *nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void init_gen2(struct device *nb_dev, struct device *dev, u8 port);</span><br><span> void sr56x0_lock_hwinitreg(void);</span><br><span> struct resource * sr5650_retrieve_cpu_mmio_resource(void);</span><br><span> #endif /* __SR5650_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26404">change 26404</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26404"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I91dfbba3c734218baf4f2de3cf88066d657096c1 </div>
<div style="display:none"> Gerrit-Change-Number: 26404 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>