<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26409">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/amd8111: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I143617bb1a4ab1812ec50155861ae2f75060851b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/amd8111/ac97.c<br>M src/southbridge/amd/amd8111/acpi.c<br>M src/southbridge/amd/amd8111/amd8111.c<br>M src/southbridge/amd/amd8111/amd8111.h<br>M src/southbridge/amd/amd8111/ide.c<br>M src/southbridge/amd/amd8111/lpc.c<br>M src/southbridge/amd/amd8111/nic.c<br>M src/southbridge/amd/amd8111/smbus.c<br>M src/southbridge/amd/amd8111/usb.c<br>M src/southbridge/amd/amd8111/usb2.c<br>10 files changed, 23 insertions(+), 23 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/26409/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c</span><br><span>index f49c9bf..fa14f9c 100644</span><br><span>--- a/src/southbridge/amd/amd8111/ac97.c</span><br><span>+++ b/src/southbridge/amd/amd8111/ac97.c</span><br><span>@@ -8,7 +8,7 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include "amd8111.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>         pci_write_config32(dev, 0x2c,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c</span><br><span>index fd3fe49..11c3963 100644</span><br><span>--- a/src/southbridge/amd/amd8111/acpi.c</span><br><span>+++ b/src/southbridge/amd/amd8111/acpi.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #endif</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_recv_byte(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_recv_byte(struct device *dev)</span><br><span> {</span><br><span>      unsigned device;</span><br><span>     struct resource *res;</span><br><span>@@ -32,7 +32,7 @@</span><br><span>    return do_smbus_recv_byte(res->base, device);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_send_byte(device_t dev, uint8_t val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_send_byte(struct device *dev, uint8_t val)</span><br><span> {</span><br><span>   unsigned device;</span><br><span>     struct resource *res;</span><br><span>@@ -44,7 +44,7 @@</span><br><span> }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, uint8_t address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, uint8_t address)</span><br><span> {</span><br><span>      unsigned device;</span><br><span>     struct resource *res;</span><br><span>@@ -55,7 +55,7 @@</span><br><span>    return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val)</span><br><span> {</span><br><span>      unsigned device;</span><br><span>     struct resource *res;</span><br><span>@@ -66,7 +66,7 @@</span><br><span>    return do_smbus_write_byte(res->base, device, address, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 bytes, u8 *buffer)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_block_read(struct device *dev, uint8_t cmd, u8 bytes, u8 *buffer)</span><br><span> {</span><br><span>      unsigned device;</span><br><span>     struct resource *res;</span><br><span>@@ -77,7 +77,7 @@</span><br><span>    return do_smbus_block_read(res->base, device, cmd, bytes, buffer);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes, const u8 *buffer)</span><br><span> {</span><br><span>  unsigned device;</span><br><span>     struct resource *res;</span><br><span>@@ -168,7 +168,7 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void acpi_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void acpi_read_resources(struct device *dev)</span><br><span> {</span><br><span>      struct resource *resource;</span><br><span> </span><br><span>@@ -186,7 +186,7 @@</span><br><span>         resource->index = 0x58;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void acpi_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void acpi_enable_resources(struct device *dev)</span><br><span> {</span><br><span>       uint8_t byte;</span><br><span>        /* Enable the generic pci resources */</span><br><span>@@ -202,7 +202,7 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   pci_write_config32(dev, 0x7c,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c</span><br><span>index 2707ca6..c75ce0d 100644</span><br><span>--- a/src/southbridge/amd/amd8111/amd8111.c</span><br><span>+++ b/src/southbridge/amd/amd8111/amd8111.c</span><br><span>@@ -4,10 +4,10 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include "amd8111.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void amd8111_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void amd8111_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t lpc_dev;</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t bus_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *lpc_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *bus_dev;</span><br><span>      unsigned index;</span><br><span>      unsigned reg_old, reg;</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h</span><br><span>index 10df590..991f5a3 100644</span><br><span>--- a/src/southbridge/amd/amd8111/amd8111.h</span><br><span>+++ b/src/southbridge/amd/amd8111/amd8111.h</span><br><span>@@ -4,7 +4,7 @@</span><br><span> #include "chip.h"</span><br><span> </span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-void amd8111_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void amd8111_enable(struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> #ifdef __PRE_RAM__</span><br><span>diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c</span><br><span>index fec424d..8ebe228 100644</span><br><span>--- a/src/southbridge/amd/amd8111/ide.c</span><br><span>+++ b/src/southbridge/amd/amd8111/ide.c</span><br><span>@@ -40,7 +40,7 @@</span><br><span>   pci_write_config16(dev, 0x42, word);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>       pci_write_config32(dev, 0x70,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c</span><br><span>index 00c56f6..eba3850 100644</span><br><span>--- a/src/southbridge/amd/amd8111/lpc.c</span><br><span>+++ b/src/southbridge/amd/amd8111/lpc.c</span><br><span>@@ -86,7 +86,7 @@</span><br><span>   enable_hpet(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8111_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8111_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>      struct resource *res;</span><br><span> </span><br><span>@@ -112,7 +112,7 @@</span><br><span>      res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   pci_write_config32(dev, 0x70,</span><br><span>                           ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>@@ -128,7 +128,7 @@</span><br><span>       return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_acpi_fill_ssdt_generator(device_t device) {</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_acpi_fill_ssdt_generator(struct device *device) {</span><br><span> #if IS_ENABLED(CONFIG_SET_FIDVID)</span><br><span>  amd_generate_powernow(pm_base + 0x10, 6, 1);</span><br><span>         acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");</span><br><span>diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c</span><br><span>index 05ca871..a3767e2 100644</span><br><span>--- a/src/southbridge/amd/amd8111/nic.c</span><br><span>+++ b/src/southbridge/amd/amd8111/nic.c</span><br><span>@@ -63,7 +63,7 @@</span><br><span>       printk(BIOS_DEBUG, "Done\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    pci_write_config32(dev, 0xc8,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c</span><br><span>index def1377..df5d73a 100644</span><br><span>--- a/src/southbridge/amd/amd8111/smbus.c</span><br><span>+++ b/src/southbridge/amd/amd8111/smbus.c</span><br><span>@@ -11,7 +11,7 @@</span><br><span> #include "amd8111.h"</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        pci_write_config32(dev, 0x44,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c</span><br><span>index feb7793..7160fb1 100644</span><br><span>--- a/src/southbridge/amd/amd8111/usb.c</span><br><span>+++ b/src/southbridge/amd/amd8111/usb.c</span><br><span>@@ -10,7 +10,7 @@</span><br><span> #include "amd8111.h"</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        pci_write_config32(dev, 0x70,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c</span><br><span>index 7a354d6..8526dc3 100644</span><br><span>--- a/src/southbridge/amd/amd8111/usb2.c</span><br><span>+++ b/src/southbridge/amd/amd8111/usb2.c</span><br><span>@@ -9,7 +9,7 @@</span><br><span> </span><br><span> #if 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>       pci_write_config32(dev, 0x70,</span><br><span>                ((device & 0xffff) << 16) | (vendor & 0xffff));</span><br><span>@@ -21,7 +21,7 @@</span><br><span> </span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8111_usb2_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8111_usb2_enable(struct device *dev)</span><br><span> {</span><br><span>   // Due to buggy USB2 we force it to disable.</span><br><span>         dev->enabled = 0;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26409">change 26409</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26409"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I143617bb1a4ab1812ec50155861ae2f75060851b </div>
<div style="display:none"> Gerrit-Change-Number: 26409 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>