<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26418">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/rs690: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I818f808e1cd8b156158251724352f8be6041030c<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/rs690/cmn.c<br>M src/southbridge/amd/rs690/gfx.c<br>M src/southbridge/amd/rs690/ht.c<br>M src/southbridge/amd/rs690/pcie.c<br>M src/southbridge/amd/rs690/rs690.c<br>M src/southbridge/amd/rs690/rs690.h<br>6 files changed, 86 insertions(+), 86 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/26418/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c</span><br><span>index 7ef9ac0..026078f 100644</span><br><span>--- a/src/southbridge/amd/rs690/cmn.c</span><br><span>+++ b/src/southbridge/amd/rs690/cmn.c</span><br><span>@@ -26,13 +26,13 @@</span><br><span> #include <delay.h></span><br><span> #include "rs690.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)</span><br><span> {</span><br><span>    pci_write_config32(dev, index_reg, index);</span><br><span>   return pci_read_config32(dev, index_reg + 0x4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static void nb_write_index(struct device *dev, u32 index_reg, u32 index, u32 data)</span><br><span> {</span><br><span> </span><br><span>    pci_write_config32(dev, index_reg, index);</span><br><span>@@ -41,7 +41,7 @@</span><br><span> }</span><br><span> </span><br><span> /* extension registers */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)</span><br><span> {</span><br><span>    /* get BAR3 base address for nbcfg0x1c */</span><br><span>    u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;</span><br><span>@@ -52,7 +52,7 @@</span><br><span>   return *((u32 *) addr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>      u32 reg_old, reg;</span><br><span> </span><br><span>@@ -71,57 +71,57 @@</span><br><span>  }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbmisc_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbmisc_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>    return nb_read_index((nb_dev), NBMISC_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>       nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_p_read_index(device_t dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_p_read_index(struct device *dev, u32 index)</span><br><span> {</span><br><span>      return nb_read_index((dev), NBPCIE_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_p_write_index(device_t dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)</span><br><span> {</span><br><span>    nb_write_index((dev), NBPCIE_INDEX, (index), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>        return nb_read_index((nb_dev), NBPCIE_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>       nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 htiu_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 htiu_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>         return nb_read_index((nb_dev), NBHTIU_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void htiu_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void htiu_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>   nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbmc_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbmc_read_index(struct device *nb_dev, u32 index)</span><br><span> {</span><br><span>       return nb_read_index((nb_dev), NBMC_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void nbmc_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span> {</span><br><span>     nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>  u32 reg_old, reg;</span><br><span>    reg = reg_old = pci_read_config32(nb_dev, reg_pos);</span><br><span>@@ -132,7 +132,7 @@</span><br><span>    }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask, u8 val)</span><br><span> {</span><br><span>        u8 reg_old, reg;</span><br><span>     reg = reg_old = pci_read_config8(nb_dev, reg_pos);</span><br><span>@@ -143,7 +143,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>  u32 reg_old, reg;</span><br><span>    reg = reg_old = nbmc_read_index(nb_dev, reg_pos);</span><br><span>@@ -154,7 +154,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>  u32 reg_old, reg;</span><br><span>    reg = reg_old = htiu_read_index(nb_dev, reg_pos);</span><br><span>@@ -165,7 +165,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>      u32 reg_old, reg;</span><br><span>    reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);</span><br><span>@@ -176,7 +176,7 @@</span><br><span>    }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>        u32 reg_old, reg;</span><br><span>    reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);</span><br><span>@@ -196,8 +196,8 @@</span><br><span> void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)</span><br><span> {</span><br><span>    /* K8 Function1 is address map */</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+        struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));</span><br><span style="color: hsl(120, 100%, 40%);">+  struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span> </span><br><span>     if (in_out) {</span><br><span>                u32 dword, sblk;</span><br><span>@@ -223,7 +223,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>      switch (port) {</span><br><span>      case 2:         /* GFX, bit4-5 */</span><br><span>@@ -246,7 +246,7 @@</span><br><span>  *   0: no device is present.</span><br><span>  *  1: device is present and is trained.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>     u16 count = 5000;</span><br><span>    u32 lc_state, reg;</span><br><span>@@ -305,7 +305,7 @@</span><br><span>  * Compliant with CIM_33's ATINB_SetToms.</span><br><span>  * Set Top Of Memory below and above 4G.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_set_tom(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_set_tom(struct device *nb_dev)</span><br><span> {</span><br><span>      /* set TOM */</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span>diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c</span><br><span>index bcba435..542394a 100644</span><br><span>--- a/src/southbridge/amd/rs690/gfx.c</span><br><span>+++ b/src/southbridge/amd/rs690/gfx.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> #define CLK_CNTL_DATA    0xC</span><br><span> </span><br><span> #ifdef UNUSED_CODE</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 clkind_read(device_t dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 clkind_read(struct device *dev, u32 index)</span><br><span> {</span><br><span>     u32     gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;</span><br><span> </span><br><span>@@ -40,7 +40,7 @@</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void clkind_write(device_t dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static void clkind_write(struct device *dev, u32 index, u32 data)</span><br><span> {</span><br><span>    u32     gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;</span><br><span>  /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */</span><br><span>@@ -53,7 +53,7 @@</span><br><span> * pci_dev_read_resources thinks it is a IO type.</span><br><span> * We have to force it to mem type.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void rs690_gfx_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void rs690_gfx_read_resources(struct device *dev)</span><br><span> {</span><br><span>        printk(BIOS_INFO, "rs690_gfx_read_resources.\n");</span><br><span> </span><br><span>@@ -106,12 +106,12 @@</span><br><span> * Set registers in RS690 and CPU to enable the internal GFX.</span><br><span> * Please refer to CIM source code and BKDG.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void rs690_internal_gfx_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void rs690_internal_gfx_enable(struct device *dev)</span><br><span> {</span><br><span>      u32 l_dword;</span><br><span>         int i;</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t k8_f2 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-     device_t nb_dev = dev_find_slot(0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+        struct device *k8_f2 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *nb_dev = dev_find_slot(0, 0);</span><br><span> </span><br><span>     printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,</span><br><span>                   nb_dev);</span><br><span>@@ -218,7 +218,7 @@</span><br><span> };</span><br><span> </span><br><span> /* step 12 ~ step 14 from rpr */</span><br><span style="color: hsl(0, 100%, 40%);">-static void single_port_configuration(device_t nb_dev, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void single_port_configuration(struct device *nb_dev, struct device *dev)</span><br><span> {</span><br><span>  u8 result, width;</span><br><span>    u32 reg32;</span><br><span>@@ -276,7 +276,7 @@</span><br><span> }</span><br><span> </span><br><span> /* step 15 ~ step 18 from rpr */</span><br><span style="color: hsl(0, 100%, 40%);">-static void dual_port_configuration(device_t nb_dev, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dual_port_configuration(struct device *nb_dev, struct device *dev)</span><br><span> {</span><br><span>         u8 result, width;</span><br><span>    u32 reg32;</span><br><span>@@ -355,10 +355,10 @@</span><br><span> * 101 = x12 (not supported)</span><br><span> *  110 = x16</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dynamic_link_width_control(struct device *nb_dev, struct device *dev, u8 width)</span><br><span> {</span><br><span>     u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sb_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sb_dev;</span><br><span>       struct southbridge_amd_rs690_config *cfg =</span><br><span>       (struct southbridge_amd_rs690_config *)nb_dev->chip_info;</span><br><span> </span><br><span>@@ -401,7 +401,7 @@</span><br><span> /*</span><br><span> * GFX Core initialization, dev2, dev3</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_gfx_init(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>   u16 reg16;</span><br><span>   struct southbridge_amd_rs690_config *cfg =</span><br><span>diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c</span><br><span>index 3c56a37..52f0d8d 100644</span><br><span>--- a/src/southbridge/amd/rs690/ht.c</span><br><span>+++ b/src/southbridge/amd/rs690/ht.c</span><br><span>@@ -22,11 +22,11 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include "rs690.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ht_dev_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void ht_dev_set_resources(struct device *dev)</span><br><span> {</span><br><span> #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)</span><br><span>        unsigned reg;</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t k8_f1;</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *k8_f1;</span><br><span>        resource_t rbase, rend;</span><br><span>      u32 base, limit;</span><br><span>     struct resource *resource;</span><br><span>@@ -59,7 +59,7 @@</span><br><span>               }</span><br><span>            if ( !(base & 3) ) {</span><br><span>                     u32 sblk;</span><br><span style="color: hsl(0, 100%, 40%);">-                       device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+                        struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span>                         /* Remember this resource has been stored. */</span><br><span>                        resource->flags |= IORESOURCE_STORED;</span><br><span>                     report_resource_stored(dev, resource, " <mmconfig>");</span><br><span>@@ -87,7 +87,7 @@</span><br><span>    struct resource *res;</span><br><span>        resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *dev = dev_find_slot(0,PCI_DEVFN(0,0));</span><br><span>        // we report mmconf base</span><br><span>     res = probe_resource(dev, 0x1C);</span><br><span>     if ( res )</span><br><span>@@ -98,7 +98,7 @@</span><br><span>       return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ht_dev_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void ht_dev_read_resources(struct device *dev)</span><br><span> {</span><br><span> #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)</span><br><span>       struct resource *res;</span><br><span>@@ -125,9 +125,9 @@</span><br><span> }</span><br><span> </span><br><span> /* for UMA internal graphics */</span><br><span style="color: hsl(0, 100%, 40%);">-void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t k8_f0;</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *k8_f0;</span><br><span>        u8 reg;</span><br><span> </span><br><span>  k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));</span><br><span>diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c</span><br><span>index db65686..b42a6f6 100644</span><br><span>--- a/src/southbridge/amd/rs690/pcie.c</span><br><span>+++ b/src/southbridge/amd/rs690/pcie.c</span><br><span>@@ -44,10 +44,10 @@</span><br><span>     0                       /* GppPwr */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-static void ValidatePortEn(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+static void ValidatePortEn(struct device *nb_dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ValidatePortEn(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void ValidatePortEn(struct device *nb_dev)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span>@@ -56,7 +56,7 @@</span><br><span> * Compliant with CIM_33's PCIEPowerOffGppPorts</span><br><span> * Power off unused GPP lines</span><br><span> *****************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>        u32 reg;</span><br><span>     u16 state_save;</span><br><span>@@ -119,7 +119,7 @@</span><br><span> </span><br><span> /**********************************************************************</span><br><span> **********************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void switching_gpp_configurations(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span>       u32 reg;</span><br><span>     struct southbridge_amd_rs690_config *cfg =</span><br><span>@@ -164,7 +164,7 @@</span><br><span> * The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration</span><br><span> * Space to a 256MB range within the first 4GB of addressable memory.</span><br><span> *****************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void enable_pcie_bar3(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_pcie_bar3(struct device *nb_dev)</span><br><span> {</span><br><span>      printk(BIOS_DEBUG, "enable_pcie_bar3()\n");</span><br><span>        set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);      /* Enables writes to the BAR3 register. */</span><br><span>@@ -180,7 +180,7 @@</span><br><span> * We should disable bar3 when we want to exit rs690_enable, because bar3 will be</span><br><span> * remapped in set_resource later.</span><br><span> *****************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void disable_pcie_bar3(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void disable_pcie_bar3(struct device *nb_dev)</span><br><span> {</span><br><span>   printk(BIOS_DEBUG, "disable_pcie_bar3()\n");</span><br><span>       set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);      /* Disable writes to the BAR3. */</span><br><span>@@ -197,11 +197,11 @@</span><br><span> * port:</span><br><span> *       p2p bridge number, 4-8</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)</span><br><span> {</span><br><span>        u8 reg8;</span><br><span>     u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sb_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sb_dev;</span><br><span>       struct southbridge_amd_rs690_config *cfg =</span><br><span>       (struct southbridge_amd_rs690_config *)nb_dev->chip_info;</span><br><span>     printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);</span><br><span>@@ -334,7 +334,7 @@</span><br><span> /*****************************************</span><br><span> * Compliant with CIM_33's PCIEConfigureGPPCore</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void config_gpp_core(device_t nb_dev, device_t sb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void config_gpp_core(struct device *nb_dev, struct device *sb_dev)</span><br><span> {</span><br><span>    u32 reg;</span><br><span>     struct southbridge_amd_rs690_config *cfg =</span><br><span>@@ -357,7 +357,7 @@</span><br><span> /*****************************************</span><br><span> * Compliant with CIM_33's PCIEMiscClkProg</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void pcie_config_misc_clk(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pcie_config_misc_clk(struct device *nb_dev)</span><br><span> {</span><br><span>       u32 reg;</span><br><span>     struct bus pbus; /* fake bus for dev0 fun1 */</span><br><span>diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c</span><br><span>index f0c8134..5de8cff 100644</span><br><span>--- a/src/southbridge/amd/rs690/rs690.c</span><br><span>+++ b/src/southbridge/amd/rs690/rs690.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> /*****************************************</span><br><span> * Compliant with CIM_33's ATINB_MiscClockCtrl</span><br><span> *****************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void static rs690_config_misc_clk(device_t nb_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void static rs690_config_misc_clk(struct device *nb_dev)</span><br><span> {</span><br><span>         u32 reg;</span><br><span>     u16 word;</span><br><span>@@ -100,7 +100,7 @@</span><br><span>      set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 get_vid_did(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 get_vid_did(struct device *dev)</span><br><span> {</span><br><span>        return pci_read_config32(dev, 0);</span><br><span> }</span><br><span>@@ -119,9 +119,9 @@</span><br><span> * case 0 will be called twice, one is by CPU in hypertransport.c line458,</span><br><span> * the other is by rs690.</span><br><span> ***********************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t nb_dev = 0, sb_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *nb_dev = 0, sb_dev = 0;</span><br><span>       int dev_ind;</span><br><span> </span><br><span>     printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));</span><br><span>diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h</span><br><span>index 9a2fec5..f6fe409 100644</span><br><span>--- a/src/southbridge/amd/rs690/rs690.h</span><br><span>+++ b/src/southbridge/amd/rs690/rs690.h</span><br><span>@@ -101,37 +101,37 @@</span><br><span> extern PCIE_CFG AtiPcieCfg;</span><br><span> </span><br><span> /* ----------------- export functions ----------------- */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbmisc_read_index(device_t nb_dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_p_read_index(device_t dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_p_write_index(device_t dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 htiu_read_index(device_t nb_dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void htiu_write_index(device_t nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbmc_read_index(device_t nb_dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbmc_write_index(device_t nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbmisc_read_index(struct device *nb_dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_p_read_index(struct device *dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_p_write_index(struct device *dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 htiu_read_index(struct device *nb_dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void htiu_write_index(struct device *nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbmc_read_index(struct device *nb_dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbmc_write_index(struct device *nb_dev, u32 index, u32 data);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);</span><br><span style="color: hsl(0, 100%, 40%);">-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, u32 mask, u32 val);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_set_tom(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask, u8 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_set_tom(struct device *nb_dev);</span><br><span> </span><br><span> void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);</span><br><span style="color: hsl(0, 100%, 40%);">-void enable_pcie_bar3(device_t nb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void disable_pcie_bar3(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_pcie_bar3(struct device *nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void disable_pcie_bar3(struct device *nb_dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_enable(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void config_gpp_core(device_t nb_dev, device_t sb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_enable(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void rs690_gfx_init(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void config_gpp_core(struct device *nb_dev, struct device *sb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);</span><br><span> #endif /* __RS690_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26418">change 26418</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope it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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I818f808e1cd8b156158251724352f8be6041030c </div>
<div style="display:none"> Gerrit-Change-Number: 26418 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>