<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26411">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/amd8132: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: Ia4be6e9b81fe4627d84c9ed7589a3e6ef2bcede2<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/amd8132/bridge.c<br>1 file changed, 8 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/26411/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c</span><br><span>index b546ef3..52306ab 100644</span><br><span>--- a/src/southbridge/amd/amd8132/bridge.c</span><br><span>+++ b/src/southbridge/amd/amd8132/bridge.c</span><br><span>@@ -29,9 +29,9 @@</span><br><span> #define NPUMB 0xD8   /* Non prefetchable upper memory base */</span><br><span> </span><br><span> static void amd8132_walk_children(struct bus *bus,</span><br><span style="color: hsl(0, 100%, 40%);">-      void (*visit)(device_t dev, void *ptr), void *ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+    void (*visit)(struct device *dev, void *ptr), void *ptr)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *child;</span><br><span>        for (child = bus->children; child; child = child->sibling) {</span><br><span>           if (child->path.type != DEVICE_PATH_PCI) {</span><br><span>                        continue;</span><br><span>@@ -50,7 +50,7 @@</span><br><span>        int max_func;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8132_count_dev(device_t dev, void *ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8132_count_dev(struct device *dev, void *ptr)</span><br><span> {</span><br><span>     struct amd8132_bus_info *info = ptr;</span><br><span>         /* Don't count pci bridges */</span><br><span>@@ -63,7 +63,7 @@</span><br><span> }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8132_pcix_tune_dev(device_t dev, void *ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)</span><br><span> {</span><br><span>  struct amd8132_bus_info *info = ptr;</span><br><span>         unsigned cap;</span><br><span>@@ -189,13 +189,13 @@</span><br><span>        amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8132_scan_bridge(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8132_scan_bridge(struct device *dev)</span><br><span> {</span><br><span>        do_pci_scan_bridge(dev, amd8132_scan_bus);</span><br><span> }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8132_pcix_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8132_pcix_init(struct device *dev)</span><br><span> {</span><br><span>   uint32_t dword;</span><br><span>      uint8_t byte;</span><br><span>@@ -354,7 +354,7 @@</span><br><span>  .device = 0x7458,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ioapic_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void ioapic_enable(struct device *dev)</span><br><span> {</span><br><span>       uint32_t value;</span><br><span> </span><br><span>@@ -366,7 +366,7 @@</span><br><span>    }</span><br><span>    pci_write_config32(dev, 0x44, value);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-static void amd8132_ioapic_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void amd8132_ioapic_init(struct device *dev)</span><br><span> {</span><br><span>    uint32_t dword;</span><br><span>      unsigned chip_rev;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26411">change 26411</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26411"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia4be6e9b81fe4627d84c9ed7589a3e6ef2bcede2 </div>
<div style="display:none"> Gerrit-Change-Number: 26411 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>