<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26417">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/pi/hudson: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: Iace820ad788fde7b230f63d95543470ce925b451<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/pi/hudson/early_setup.c<br>M src/southbridge/amd/pi/hudson/hudson.c<br>M src/southbridge/amd/pi/hudson/hudson.h<br>M src/southbridge/amd/pi/hudson/lpc.c<br>M src/southbridge/amd/pi/hudson/sm.c<br>5 files changed, 17 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/26417/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>index ae8b406..d95385b 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>@@ -276,7 +276,7 @@</span><br><span> static uintptr_t hudson_spibase(void)</span><br><span> {</span><br><span>     /* Make sure the base address is predictable */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(0, 0x14, 3);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_devfn_t dev = PCI_DEV(0, 0x14, 3);</span><br><span> </span><br><span>   u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)</span><br><span>                                                      & 0xfffffff0;</span><br><span>@@ -328,7 +328,7 @@</span><br><span> </span><br><span> void hudson_tpm_decode_spi(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t dev = PCI_DEV(0, 0x14, 3);     /* LPC device */</span><br><span style="color: hsl(120, 100%, 40%);">+      pci_devfn_t dev = PCI_DEV(0, 0x14, 3);  /* LPC device */</span><br><span> </span><br><span>         u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);</span><br><span>  pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c</span><br><span>index e306836..2772391 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/hudson.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/hudson.c</span><br><span>@@ -55,14 +55,14 @@</span><br><span>     return read16((void *)(PM_MMIO_BASE + reg));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void hudson_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void hudson_enable(struct device *dev)</span><br><span> {</span><br><span>   printk(BIOS_DEBUG, "hudson_enable()\n");</span><br><span>   switch (dev->path.pci.devfn) {</span><br><span>    case (0x14 << 3) | 7: /* 0:14.7  SD */</span><br><span>                 if (dev->enabled == 0) {</span><br><span>                  // read the VENDEV ID</span><br><span style="color: hsl(0, 100%, 40%);">-                   device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7));</span><br><span style="color: hsl(120, 100%, 40%);">+                     struct device *sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7));</span><br><span>                      u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16;</span><br><span>                        /* turn off the SDHC controller in the PM reg */</span><br><span>                     u8 reg8;</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>index 2ccd485..091464f 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>+++ b/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>@@ -197,7 +197,7 @@</span><br><span> #endif</span><br><span> </span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-void hudson_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void hudson_enable(struct device *dev);</span><br><span> void s3_resume_init_data(void *FchParams);</span><br><span> </span><br><span> #endif /* __PRE_RAM__ */</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c</span><br><span>index da51cd0..587fd95 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/lpc.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/lpc.c</span><br><span>@@ -31,11 +31,11 @@</span><br><span> #include "hudson.h"</span><br><span> #include "pci_devs.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_init(struct device *dev)</span><br><span> {</span><br><span>   u8 byte;</span><br><span>     u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   /* Enable the LPC Controller */</span><br><span>      sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>@@ -93,7 +93,7 @@</span><br><span>   pm_write8(PM_SERIRQ_CONF, byte);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void hudson_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hudson_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>         struct resource *res;</span><br><span> </span><br><span>@@ -144,7 +144,7 @@</span><br><span>  * @param dev the device whose children's resources are to be enabled</span><br><span>  *</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void hudson_lpc_enable_childrens_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hudson_lpc_enable_childrens_resources(struct device *dev)</span><br><span> {</span><br><span>         struct bus *link;</span><br><span>    u32 reg, reg_x;</span><br><span>@@ -184,7 +184,7 @@</span><br><span>        reg_var[0] = pci_read_config16(dev, 0x64);</span><br><span> </span><br><span>       for (link = dev->link_list; link; link = link->next) {</span><br><span style="color: hsl(0, 100%, 40%);">-            device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+               struct device *child;</span><br><span>                for (child = link->children; child;</span><br><span>                    child = child->sibling) {</span><br><span>                    if (child->enabled</span><br><span>@@ -323,7 +323,7 @@</span><br><span>  pci_write_config8(dev, 0x74, wiosize);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void hudson_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hudson_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span>       pci_dev_enable_resources(dev);</span><br><span>       hudson_lpc_enable_childrens_resources(dev);</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c</span><br><span>index db29d10..b369155 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/sm.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/sm.c</span><br><span>@@ -41,12 +41,12 @@</span><br><span> * HUDSON enables SATA by default in SMBUS Control.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sm_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sm_init(struct device *dev)</span><br><span> {</span><br><span>        setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_recv_byte(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_recv_byte(struct device *dev)</span><br><span> {</span><br><span>       u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -60,7 +60,7 @@</span><br><span>    return do_smbus_recv_byte(res->base, device);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_send_byte(device_t dev, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_send_byte(struct device *dev, u8 val)</span><br><span> {</span><br><span>     u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -74,7 +74,7 @@</span><br><span>    return do_smbus_send_byte(res->base, device, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>        u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -88,7 +88,7 @@</span><br><span>    return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span>  u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -108,7 +108,7 @@</span><br><span>  .write_byte = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void hudson_sm_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hudson_sm_read_resources(struct device *dev)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26417">change 26417</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26417"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iace820ad788fde7b230f63d95543470ce925b451 </div>
<div style="display:none"> Gerrit-Change-Number: 26417 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>