<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26366">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">drivers/intel/gma/i915_reg.h: Fix coding style<br><br>Change-Id: Icee8ea01ca846f559f3a38da48325733407c302e<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/drivers/intel/gma/i915_reg.h<br>1 file changed, 906 insertions(+), 906 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26366/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h</span><br><span>index ae774a5..7c7269b 100644</span><br><span>--- a/src/drivers/intel/gma/i915_reg.h</span><br><span>+++ b/src/drivers/intel/gma/i915_reg.h</span><br><span>@@ -25,10 +25,10 @@</span><br><span> #ifndef _I915_REG_H_</span><br><span> #define _I915_REG_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))</span><br><span style="color: hsl(0, 100%, 40%);">-#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define _PIPE(pipe, a, b) ((a) + (pipe)*((b) - (a)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b) - (a)))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define _PORT(port, a, b) ((a) + (port)*((b) - (a)))</span><br><span> </span><br><span> #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))</span><br><span> #define _MASKED_BIT_DISABLE(a) ((a) << 16)</span><br><span>@@ -88,18 +88,18 @@</span><br><span> /* Graphics reset regs */</span><br><span> #define I965_GDRST 0xc0 /* PCI config register */</span><br><span> #define ILK_GDSR 0x2ca4 /* MCHBAR offset */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GRDOM_FULL (0<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GRDOM_RENDER (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GRDOM_MEDIA (3<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GRDOM_RESET_ENABLE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRDOM_FULL (0 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRDOM_RENDER (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRDOM_MEDIA (3 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRDOM_RESET_ENABLE (1 << 0)</span><br><span> </span><br><span> #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */</span><br><span> #define GEN6_MBC_SNPCR_SHIFT 21</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_MBC_SNPCR_MASK (3<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_MBC_SNPCR_MAX (0<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_MBC_SNPCR_MED (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_MBC_SNPCR_LOW (2<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_MBC_SNPCR_MASK (3 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_MBC_SNPCR_MAX (0 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_MBC_SNPCR_MED (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_MBC_SNPCR_LOW (2 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */</span><br><span> </span><br><span> #define GEN6_MBCTL 0x0907c</span><br><span> #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)</span><br><span>@@ -114,22 +114,22 @@</span><br><span> #define GEN6_GRDOM_MEDIA (1 << 2)</span><br><span> #define GEN6_GRDOM_BLT (1 << 3)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base + 0x228)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base + 0x518)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base + 0x220)</span><br><span> #define PP_DIR_DCLV_2G 0xffffffff</span><br><span> </span><br><span> #define GAM_ECOCHK 0x4090</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECOCHK_SNB_BIT (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECOCHK_PPGTT_CACHE64B (0x3<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECOCHK_PPGTT_CACHE4B (0x0<<3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECOCHK_SNB_BIT (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)</span><br><span> </span><br><span> #define GAC_ECO_BITS 0x14090</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECOBITS_PPGTT_CACHE64B (3<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECOBITS_PPGTT_CACHE4B (0<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECOBITS_PPGTT_CACHE64B (3 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECOBITS_PPGTT_CACHE4B (0 << 8)</span><br><span> </span><br><span> #define GAB_CTL 0x24000</span><br><span style="color: hsl(0, 100%, 40%);">-#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)</span><br><span> </span><br><span> /* VGA stuff */</span><br><span> </span><br><span>@@ -138,14 +138,14 @@</span><br><span> </span><br><span> #define VGA_MSR_WRITE 0x3c2</span><br><span> #define VGA_MSR_READ 0x3cc</span><br><span style="color: hsl(0, 100%, 40%);">-#define VGA_MSR_MEM_EN (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define VGA_MSR_CGA_MODE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define VGA_MSR_MEM_EN (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define VGA_MSR_CGA_MODE (1 << 0)</span><br><span> </span><br><span> #define VGA_SR_INDEX 0x3c4</span><br><span> #define VGA_SR_DATA 0x3c5</span><br><span> </span><br><span> #define VGA_AR_INDEX 0x3c0</span><br><span style="color: hsl(0, 100%, 40%);">-#define VGA_AR_VID_EN (1<<5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define VGA_AR_VID_EN (1 << 5)</span><br><span> #define VGA_AR_DATA_WRITE 0x3c0</span><br><span> #define VGA_AR_DATA_READ 0x3c1</span><br><span> </span><br><span>@@ -180,10 +180,10 @@</span><br><span> #define MI_NOOP MI_INSTR(0, 0)</span><br><span> #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)</span><br><span> #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_WAIT_FOR_OVERLAY_FLIP (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_WAIT_FOR_PLANE_B_FLIP (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_WAIT_FOR_PLANE_A_FLIP (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1 << 1)</span><br><span> #define MI_FLUSH MI_INSTR(0x04, 0)</span><br><span> #define MI_READ_FLUSH (1 << 0)</span><br><span> #define MI_EXE_FLUSH (1 << 1)</span><br><span>@@ -193,12 +193,12 @@</span><br><span> #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */</span><br><span> #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)</span><br><span> #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SUSPEND_FLUSH_EN (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SUSPEND_FLUSH_EN (1 << 0)</span><br><span> #define MI_REPORT_HEAD MI_INSTR(0x07, 0)</span><br><span> #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_OVERLAY_CONTINUE (0x0<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_OVERLAY_ON (0x1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_OVERLAY_OFF (0x2<<21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_OVERLAY_CONTINUE (0x0 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_OVERLAY_ON (0x1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_OVERLAY_OFF (0x2 << 21)</span><br><span> #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)</span><br><span> #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)</span><br><span> #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)</span><br><span>@@ -211,16 +211,16 @@</span><br><span> #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)</span><br><span> #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)</span><br><span> #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_ARB_ENABLE (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_ARB_DISABLE (0<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_ARB_ENABLE (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_ARB_DISABLE (0 << 0)</span><br><span> </span><br><span> #define MI_SET_CONTEXT MI_INSTR(0x18, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_MM_SPACE_GTT (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_MM_SPACE_PHYSICAL (0<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SAVE_EXT_STATE_EN (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_RESTORE_EXT_STATE_EN (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_FORCE_RESTORE (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_RESTORE_INHIBIT (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_MM_SPACE_GTT (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_MM_SPACE_PHYSICAL (0 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SAVE_EXT_STATE_EN (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_RESTORE_EXT_STATE_EN (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_FORCE_RESTORE (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_RESTORE_INHIBIT (1 << 0)</span><br><span> #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)</span><br><span> #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */</span><br><span> #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)</span><br><span>@@ -233,99 +233,99 @@</span><br><span> */</span><br><span> #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)</span><br><span> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_FLUSH_DW_STORE_INDEX (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_INVALIDATE_TLB (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_FLUSH_DW_OP_STOREDW (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_INVALIDATE_BSD (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_FLUSH_DW_USE_GTT (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_FLUSH_DW_USE_PPGTT (0<<2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_FLUSH_DW_STORE_INDEX (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_INVALIDATE_TLB (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_FLUSH_DW_OP_STOREDW (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_INVALIDATE_BSD (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_FLUSH_DW_USE_GTT (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_FLUSH_DW_USE_PPGTT (0 << 2)</span><br><span> #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)</span><br><span> #define MI_BATCH_NON_SECURE (1)</span><br><span> /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_BATCH_NON_SECURE_I965 (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_BATCH_PPGTT_HSW (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_BATCH_NON_SECURE_HSW (1<<13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_BATCH_NON_SECURE_I965 (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_BATCH_PPGTT_HSW (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_BATCH_NON_SECURE_HSW (1 << 13)</span><br><span> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_BATCH_GTT (2 << 6) /* aliased with (1 << 7) on gen4 */</span><br><span> #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_UPDATE (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_COMPARE (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_REGISTER (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_RV (2<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_RB (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_VR (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_VB (2<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_BR (2<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_BV (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_SEMAPHORE_SYNC_INVALID (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_GLOBAL_GTT (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_UPDATE (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_COMPARE (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_REGISTER (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_RV (2 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_RB (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_VR (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_VB (2 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_BR (2 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_BV (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_SEMAPHORE_SYNC_INVALID (1 << 0)</span><br><span> /*</span><br><span> * 3D instructions used by the kernel</span><br><span> */</span><br><span> #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SC_UPDATE_SCISSOR (0x1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SC_ENABLE_MASK (0x1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SC_ENABLE (0x1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCI_YMIN_MASK (0xffff<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCI_XMIN_MASK (0xffff<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCI_YMAX_MASK (0xffff<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCI_XMAX_MASK (0xffff<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLT_DEPTH_8 (0<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLT_DEPTH_16_565 (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLT_DEPTH_16_1555 (2<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLT_DEPTH_32 (3<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLT_ROP_GXCOPY (0xcc<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ASYNC_FLIP (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPLAY_PLANE_A (0<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPLAY_PLANE_B (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_CS_STALL (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_QW_WRITE (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_DEPTH_STALL (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_WRITE_FLUSH (1<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_NOTIFY (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_RASTER_RULES ((0x3 << 29) | (0x7 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_SCISSOR ((0x3 << 29) | (0x1c << 24) | (0x10 << 19))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SC_UPDATE_SCISSOR (0x1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SC_ENABLE_MASK (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SC_ENABLE (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_LOAD_INDIRECT ((0x3 << 29) | (0x1d << 24) | (0x7 << 16))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_SCISSOR_INFO ((0x3 << 29) | (0x1d << 24) | (0x81 << 16) | (0x1))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_YMIN_MASK (0xffff << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_XMIN_MASK (0xffff << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_YMAX_MASK (0xffff << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_XMAX_MASK (0xffff << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_SCISSOR_ENABLE ((0x3 << 29) | (0x1c << 24) | (0x10 << 19))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_SCISSOR_RECT ((0x3 << 29) | (0x1d << 24) | (0x81 << 16) | 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_COLOR_FACTOR ((0x3 << 29) | (0x1d << 24) | (0x1 << 16) | 0x0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_STIPPLE ((0x3 << 29) | (0x1d << 24) | (0x83 << 16))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_MAP_INFO ((0x3 << 29) | (0x1d << 24) | 0x4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_DESTBUFFER_VARS ((0x3 << 29) | (0x1d << 24) | (0x85 << 16) | 0x0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_DESTBUFFER_INFO ((0x3 << 29) | (0x1d << 24) | (0x8e << 16) | 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_DRAWRECT_INFO ((0x3 << 29) | (0x1d << 24) | (0x80 << 16) | (0x3))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900 << 16)|0x2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define XY_MONO_SRC_COPY_IMM_BLT ((2 << 29) | (0x71 << 22) | 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define XY_SRC_COPY_BLT_WRITE_ALPHA (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define XY_SRC_COPY_BLT_WRITE_RGB (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLT_DEPTH_8 (0 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLT_DEPTH_16_565 (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLT_DEPTH_16_1555 (2 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLT_DEPTH_32 (3 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLT_ROP_GXCOPY (0xcc << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define XY_SRC_COPY_BLT_SRC_TILED (1 << 15) /* 965+ only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define XY_SRC_COPY_BLT_DST_TILED (1 << 11) /* 965+ only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0 << 29) | (0x14 << 23)|2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ASYNC_FLIP (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPLAY_PLANE_A (0 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPLAY_PLANE_B (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_OP_PIPE_CONTROL(len) ((0x3 << 29) | (0x3 << 27) | (0x2 << 24) | (len-2))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_CS_STALL (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_TLB_INVALIDATE (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_QW_WRITE (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_DEPTH_STALL (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_WRITE_FLUSH (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1 << 12) /* gen6+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1 << 11) /* MBZ on Ironlake */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1 << 10) /* GM45+ only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_NOTIFY (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CONTROL_GLOBAL_GTT (1 << 2) /* in addr dword */</span><br><span> </span><br><span> </span><br><span> /*</span><br><span> * Reset registers</span><br><span> */</span><br><span> #define DEBUG_RESET_I830 0x6070</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEBUG_RESET_FULL (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEBUG_RESET_RENDER (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEBUG_RESET_DISPLAY (1<<9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEBUG_RESET_FULL (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEBUG_RESET_RENDER (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEBUG_RESET_DISPLAY (1 << 9)</span><br><span> </span><br><span> /*</span><br><span> * DPIO - a special bus for various display related registers to hide behind:</span><br><span>@@ -337,19 +337,19 @@</span><br><span> * 0x8100: fast clock controls</span><br><span> */</span><br><span> #define DPIO_PKT 0x2100</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_RID (0<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_OP_WRITE (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_OP_READ (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_PORTID (0x12<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_BYTE (0xf<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_BUSY (1<<0) /* status only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_RID (0 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_OP_WRITE (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_OP_READ (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_PORTID (0x12 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_BYTE (0xf << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_BUSY (1 << 0) /* status only */</span><br><span> #define DPIO_DATA 0x2104</span><br><span> #define DPIO_REG 0x2108</span><br><span> #define DPIO_CTL 0x2110</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_SFR_BYPASS (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_RESET (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_SFR_BYPASS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_RESET (1 << 0)</span><br><span> </span><br><span> #define _DPIO_DIV_A 0x800c</span><br><span> #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */</span><br><span>@@ -357,7 +357,7 @@</span><br><span> #define DPIO_P1_SHIFT (21) /* 3 bits */</span><br><span> #define DPIO_P2_SHIFT (16) /* 5 bits */</span><br><span> #define DPIO_N_SHIFT (12) /* 4 bits */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPIO_ENABLE_CALIBRATION (1<<11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPIO_ENABLE_CALIBRATION (1 << 11)</span><br><span> #define DPIO_M1DIV_SHIFT (8) /* 3 bits */</span><br><span> #define DPIO_M2DIV_MASK 0xff</span><br><span> #define _DPIO_DIV_B 0x802c</span><br><span>@@ -396,10 +396,10 @@</span><br><span> #define I830_FENCE_TILING_Y_SHIFT 12</span><br><span> #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)</span><br><span> #define I830_FENCE_PITCH_SHIFT 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define I830_FENCE_REG_VALID (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I830_FENCE_REG_VALID (1 << 0)</span><br><span> #define I915_FENCE_MAX_PITCH_VAL 4</span><br><span> #define I830_FENCE_MAX_PITCH_VAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define I830_FENCE_MAX_SIZE_VAL (1<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I830_FENCE_MAX_SIZE_VAL (1 << 8)</span><br><span> </span><br><span> #define I915_FENCE_START_MASK 0x0ff00000</span><br><span> #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)</span><br><span>@@ -407,7 +407,7 @@</span><br><span> #define FENCE_REG_965_0 0x03000</span><br><span> #define I965_FENCE_PITCH_SHIFT 2</span><br><span> #define I965_FENCE_TILING_Y_SHIFT 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define I965_FENCE_REG_VALID (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I965_FENCE_REG_VALID (1 << 0)</span><br><span> #define I965_FENCE_MAX_PITCH_VAL 0x0400</span><br><span> </span><br><span> #define FENCE_REG_SANDYBRIDGE_0 0x100000</span><br><span>@@ -427,33 +427,33 @@</span><br><span> #define BSD_RING_BASE 0x04000</span><br><span> #define GEN6_BSD_RING_BASE 0x12000</span><br><span> #define BLT_RING_BASE 0x22000</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_TAIL(base) ((base)+0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_HEAD(base) ((base)+0x34)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_START(base) ((base)+0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_CTL(base) ((base)+0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_SYNC_0(base) ((base)+0x40)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_SYNC_1(base) ((base)+0x44)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_TAIL(base) ((base) + 0x30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_HEAD(base) ((base) + 0x34)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_START(base) ((base) + 0x38)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_CTL(base) ((base) + 0x3c)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_SYNC_0(base) ((base) + 0x40)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_SYNC_1(base) ((base) + 0x44)</span><br><span> #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))</span><br><span> #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))</span><br><span> #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))</span><br><span> #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))</span><br><span> #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))</span><br><span> #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_MAX_IDLE(base) ((base)+0x54)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_HWS_PGA(base) ((base)+0x80)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_MAX_IDLE(base) ((base) + 0x54)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_HWS_PGA(base) ((base) + 0x80)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_HWS_PGA_GEN6(base) ((base) + 0x2080)</span><br><span> #define ARB_MODE 0x04030</span><br><span style="color: hsl(0, 100%, 40%);">-#define ARB_MODE_SWIZZLE_SNB (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ARB_MODE_SWIZZLE_IVB (1<<5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ARB_MODE_SWIZZLE_SNB (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ARB_MODE_SWIZZLE_IVB (1 << 5)</span><br><span> #define RENDER_HWS_PGA_GEN7 (0x04080)</span><br><span> #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)</span><br><span> #define DONE_REG 0x40b0</span><br><span> #define BSD_HWS_PGA_GEN7 (0x04180)</span><br><span> #define BLT_HWS_PGA_GEN7 (0x04280)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_ACTHD(base) ((base)+0x74)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_NOPID(base) ((base)+0x94)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_IMR(base) ((base)+0xa8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_TIMESTAMP(base) ((base)+0x358)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_ACTHD(base) ((base) + 0x74)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_NOPID(base) ((base) + 0x94)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_IMR(base) ((base) + 0xa8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_TIMESTAMP(base) ((base) + 0x358)</span><br><span> #define TAIL_ADDR 0x001FFFF8</span><br><span> #define HEAD_WRAP_COUNT 0xFFE00000</span><br><span> #define HEAD_WRAP_ONE 0x00200000</span><br><span>@@ -466,9 +466,9 @@</span><br><span> #define RING_VALID_MASK 0x00000001</span><br><span> #define RING_VALID 0x00000001</span><br><span> #define RING_INVALID 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */</span><br><span> #if 0</span><br><span> #define PRB0_TAIL 0x02030</span><br><span> #define PRB0_HEAD 0x02034</span><br><span>@@ -487,12 +487,12 @@</span><br><span> #define GEN7_SAMPLER_INSTDONE 0x0e160</span><br><span> #define GEN7_ROW_INSTDONE 0x0e164</span><br><span> #define I915_NUM_INSTDONE_REG 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_IPEIR(base) ((base)+0x64)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_IPEHR(base) ((base)+0x68)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_INSTDONE(base) ((base)+0x6c)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_INSTPS(base) ((base)+0x70)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_DMA_FADD(base) ((base)+0x78)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_INSTPM(base) ((base)+0xc0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_IPEIR(base) ((base) + 0x64)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_IPEHR(base) ((base) + 0x68)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_INSTDONE(base) ((base) + 0x6c)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_INSTPS(base) ((base) + 0x70)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_DMA_FADD(base) ((base) + 0x78)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_INSTPM(base) ((base) + 0xc0)</span><br><span> #define INSTPS 0x02070 /* 965+ only */</span><br><span> #define INSTDONE1 0x0207c /* 965+ only */</span><br><span> #define ACTHD_I965 0x02074</span><br><span>@@ -500,7 +500,7 @@</span><br><span> #define HWS_ADDRESS_MASK 0xfffff000</span><br><span> #define HWS_START_ADDRESS_SHIFT 4</span><br><span> #define PWRCTXA 0x2088 /* 965GM+ only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PWRCTX_EN (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRCTX_EN (1 << 0)</span><br><span> #define IPEIR 0x02088</span><br><span> #define IPEHR 0x0208c</span><br><span> #define INSTDONE 0x02090</span><br><span>@@ -510,7 +510,7 @@</span><br><span> </span><br><span> #define ERROR_GEN6 0x040a0</span><br><span> #define GEN7_ERR_INT 0x44040</span><br><span style="color: hsl(0, 100%, 40%);">-#define ERR_INT_MMIO_UNCLAIMED (1<<13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ERR_INT_MMIO_UNCLAIMED (1 << 13)</span><br><span> </span><br><span> #define DERRMR 0x44050</span><br><span> </span><br><span>@@ -541,13 +541,13 @@</span><br><span> </span><br><span> #define GFX_MODE 0x02520</span><br><span> #define GFX_MODE_GEN7 0x0229c</span><br><span style="color: hsl(0, 100%, 40%);">-#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_RUN_LIST_ENABLE (1<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_SURFACE_FAULT_ENABLE (1<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_REPLAY_MODE (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_PSMI_GRANULARITY (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_PPGTT_ENABLE (1<<9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RING_MODE_GEN7(ring) ((ring)->mmio_base + 0x29c)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_RUN_LIST_ENABLE (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_TLB_INVALIDATE_ALWAYS (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_SURFACE_FAULT_ENABLE (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_REPLAY_MODE (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_PSMI_GRANULARITY (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_PPGTT_ENABLE (1 << 9)</span><br><span> </span><br><span> #define VLV_DISPLAY_BASE 0x180000</span><br><span> </span><br><span>@@ -557,52 +557,52 @@</span><br><span> #define IMR 0x020a8</span><br><span> #define ISR 0x020ac</span><br><span> #define VLV_GUNIT_CLOCK_GATE 0x182060</span><br><span style="color: hsl(0, 100%, 40%);">-#define GCFG_DIS (1<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCFG_DIS (1 << 8)</span><br><span> #define VLV_IIR_RW 0x182084</span><br><span> #define VLV_IER 0x1820a0</span><br><span> #define VLV_IIR 0x1820a4</span><br><span> #define VLV_IMR 0x1820a8</span><br><span> #define VLV_ISR 0x1820ac</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PORT_INTERRUPT (1<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_HWB_OOM_INTERRUPT (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_SYNC_STATUS_INTERRUPT (1<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_DEBUG_INTERRUPT (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_USER_INTERRUPT (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_ASLE_INTERRUPT (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_BSD_USER_INTERRUPT (1<<25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_HWB_OOM_INTERRUPT (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_SYNC_STATUS_INTERRUPT (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_DEBUG_INTERRUPT (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_USER_INTERRUPT (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_ASLE_INTERRUPT (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_BSD_USER_INTERRUPT (1 << 25)</span><br><span> #define EIR 0x020b0</span><br><span> #define EMR 0x020b4</span><br><span> #define ESR 0x020b8</span><br><span style="color: hsl(0, 100%, 40%);">-#define GM45_ERROR_PAGE_TABLE (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GM45_ERROR_MEM_PRIV (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_ERROR_PAGE_TABLE (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GM45_ERROR_CP_PRIV (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_ERROR_MEMORY_REFRESH (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I915_ERROR_INSTRUCTION (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GM45_ERROR_PAGE_TABLE (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GM45_ERROR_MEM_PRIV (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_ERROR_PAGE_TABLE (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GM45_ERROR_CP_PRIV (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_ERROR_MEMORY_REFRESH (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I915_ERROR_INSTRUCTION (1 << 0)</span><br><span> #define INSTPM 0x020c0</span><br><span style="color: hsl(0, 100%, 40%);">-#define INSTPM_SELF_EN (1<<12) /* 915GM only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTPM_SELF_EN (1 << 12) /* 915GM only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTPM_AGPBUSY_DIS (1 << 11) /* gen3: when disabled, pending interrupts</span><br><span> will not assert AGPBUSY# and will only</span><br><span> be delivered when out of C3. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */</span><br><span> #define ACTHD 0x020c8</span><br><span> #define FW_BLC 0x020d8</span><br><span> #define FW_BLC2 0x020dc</span><br><span> #define FW_BLC_SELF 0x020e0 /* 915+ only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FW_BLC_SELF_EN_MASK (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FW_BLC_SELF_EN (1<<15) /* 945 only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FW_BLC_SELF_EN_MASK (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FW_BLC_SELF_EN (1 << 15) /* 945 only */</span><br><span> #define MM_BURST_LENGTH 0x00700000</span><br><span> #define MM_FIFO_WATERMARK 0x0001F000</span><br><span> #define LM_BURST_LENGTH 0x00000700</span><br><span>@@ -672,24 +672,24 @@</span><br><span> #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */</span><br><span> </span><br><span> #define CACHE_MODE_0 0x02120 /* 915+ only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_IZ_OPT_DISABLE (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_ZR_OPT_DISABLE (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_DEPTH_EVICT_DISABLE (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_COLOR_EVICT_DISABLE (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_DEPTH_WRITE_DISABLE (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CM0_RC_OP_FLUSH_DISABLE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_IZ_OPT_DISABLE (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_ZR_OPT_DISABLE (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_DEPTH_EVICT_DISABLE (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_COLOR_EVICT_DISABLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_DEPTH_WRITE_DISABLE (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)</span><br><span> #define BB_ADDR 0x02140 /* 8 bytes */</span><br><span> #define GFX_FLSH_CNTL 0x02170 /* 915+ only */</span><br><span> #define GFX_FLSH_CNTL_GEN6 0x101008</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_FLSH_CNTL_EN (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GFX_FLSH_CNTL_EN (1 << 0)</span><br><span> #define ECOSKPD 0x021d0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECO_GATING_CX_ONLY (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECO_FLIP_DONE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECO_GATING_CX_ONLY (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECO_FLIP_DONE (1 << 0)</span><br><span> </span><br><span> #define CACHE_MODE_1 0x7004 /* IVB+ */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)</span><br><span> </span><br><span> /* GEN6 interrupt control</span><br><span> * Note that the per-ring interrupt bits do alias with the global interrupt bits</span><br><span>@@ -715,7 +715,7 @@</span><br><span> </span><br><span> #define GEN6_BLITTER_ECOSKPD 0x221d0</span><br><span> #define GEN6_BLITTER_LOCK_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_BLITTER_FBC_NOTIFY (1<<3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)</span><br><span> </span><br><span> #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050</span><br><span> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)</span><br><span>@@ -731,18 +731,18 @@</span><br><span> </span><br><span> #define GEN7_FF_THREAD_MODE 0x20a0</span><br><span> #define GEN7_FF_SCHED_MASK 0x0077070</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_VS_SCHED_HW (0x0<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_FF_DS_SCHED_HW (0x0<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_VS_SCHED_HW (0x0 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_FF_DS_SCHED_HW (0x0 << 4)</span><br><span> </span><br><span> /*</span><br><span> * Framebuffer compression (915+ only)</span><br><span>@@ -751,29 +751,29 @@</span><br><span> #define FBC_CFB_BASE 0x03200 /* 4k page aligned */</span><br><span> #define FBC_LL_BASE 0x03204 /* 4k page aligned */</span><br><span> #define FBC_CONTROL 0x03208</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_EN (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_PERIODIC (1<<30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_EN (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_PERIODIC (1 << 30)</span><br><span> #define FBC_CTL_INTERVAL_SHIFT (16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_UNCOMPRESSIBLE (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_C3_IDLE (1<<13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_UNCOMPRESSIBLE (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_C3_IDLE (1 << 13)</span><br><span> #define FBC_CTL_STRIDE_SHIFT (5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_FENCENO (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_FENCENO (1 << 0)</span><br><span> #define FBC_COMMAND 0x0320c</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CMD_COMPRESS (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CMD_COMPRESS (1 << 0)</span><br><span> #define FBC_STATUS 0x03210</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_STAT_COMPRESSING (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_STAT_COMPRESSED (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_STAT_MODIFIED (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_STAT_CURRENT_LINE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_STAT_COMPRESSING (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_STAT_COMPRESSED (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_STAT_MODIFIED (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_STAT_CURRENT_LINE (1 << 0)</span><br><span> #define FBC_CONTROL2 0x03214</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_FENCE_DBL (0<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_IDLE_IMM (0<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_IDLE_FULL (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_IDLE_LINE (2<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_IDLE_DEBUG (3<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_CPU_FENCE (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_PLANEA (0<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FBC_CTL_PLANEB (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_FENCE_DBL (0 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_IDLE_IMM (0 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_IDLE_FULL (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_IDLE_LINE (2 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_IDLE_DEBUG (3 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_CPU_FENCE (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_PLANEA (0 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FBC_CTL_PLANEB (1 << 0)</span><br><span> #define FBC_FENCE_OFF 0x0321b</span><br><span> #define FBC_TAG 0x03300</span><br><span> </span><br><span>@@ -782,17 +782,17 @@</span><br><span> /* Framebuffer compression for GM45+ */</span><br><span> #define DPFC_CB_BASE 0x3200</span><br><span> #define DPFC_CONTROL 0x3208</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_EN (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_PLANEA (0<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_PLANEB (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_FENCE_EN (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_PERSISTENT_MODE (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_SR_EN (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_LIMIT_1X (0<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_LIMIT_2X (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_CTL_LIMIT_4X (2<<6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_EN (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_PLANEA (0 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_PLANEB (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_FENCE_EN (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_PERSISTENT_MODE (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_SR_EN (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_LIMIT_1X (0 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_LIMIT_2X (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_CTL_LIMIT_4X (2 << 6)</span><br><span> #define DPFC_RECOMP_CTL 0x320c</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_RECOMP_STALL_EN (1<<27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_RECOMP_STALL_EN (1 << 27)</span><br><span> #define DPFC_RECOMP_STALL_WM_SHIFT (16)</span><br><span> #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)</span><br><span> #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)</span><br><span>@@ -805,7 +805,7 @@</span><br><span> #define DPFC_STATUS2 0x3214</span><br><span> #define DPFC_FENCE_YOFF 0x3218</span><br><span> #define DPFC_CHICKEN 0x3224</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPFC_HT_MODIFY (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPFC_HT_MODIFY (1UL << 31)</span><br><span> </span><br><span> /* Framebuffer compression for Ironlake */</span><br><span> #define ILK_DPFC_CB_BASE 0x43200</span><br><span>@@ -817,11 +817,11 @@</span><br><span> #define ILK_DPFC_FENCE_YOFF 0x43218</span><br><span> #define ILK_DPFC_CHICKEN 0x43224</span><br><span> #define ILK_FBC_RT_BASE 0x2128</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_FBC_RT_VALID (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_FBC_RT_VALID (1 << 0)</span><br><span> </span><br><span> #define ILK_DISPLAY_CHICKEN1 0x42000</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_FBCQ_DIS (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_PABSTRETCH_DIS (1<<21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_FBCQ_DIS (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_PABSTRETCH_DIS (1 << 21)</span><br><span> </span><br><span> </span><br><span> /*</span><br><span>@@ -830,7 +830,7 @@</span><br><span> * The following two registers are of type GTTMMADR</span><br><span> */</span><br><span> #define SNB_DPFC_CTL_SA 0x100100</span><br><span style="color: hsl(0, 100%, 40%);">-#define SNB_CPU_FENCE_ENABLE (1<<29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SNB_CPU_FENCE_ENABLE (1 << 29)</span><br><span> #define DPFC_CPU_FENCE_OFFSET 0x100104</span><br><span> </span><br><span> </span><br><span>@@ -861,12 +861,12 @@</span><br><span> # define GPIO_DATA_PULLUP_DISABLE (1 << 13)</span><br><span> </span><br><span> #define GMBUS0 0x5100 /* clock/port select */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_RATE_100KHZ (0<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_RATE_50KHZ (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_RATE_MASK (3<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_RATE_100KHZ (0 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_RATE_50KHZ (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_RATE_MASK (3 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */</span><br><span> #define GMBUS_PORT_DISABLED 0</span><br><span> #define GMBUS_PORT_SSC 1</span><br><span> #define GMBUS_PORT_VGADDC 2</span><br><span>@@ -878,35 +878,35 @@</span><br><span> #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)</span><br><span> #define GMBUS_PORT_MASK 7</span><br><span> #define GMBUS1 0x5104 /* command/status */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_SW_CLR_INT (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_SW_RDY (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_ENT (1<<29) /* enable timeout */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_CYCLE_NONE (0<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_CYCLE_WAIT (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_CYCLE_INDEX (2<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_CYCLE_STOP (4<<25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_SW_CLR_INT (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_SW_RDY (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_ENT (1 << 29) /* enable timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_CYCLE_NONE (0 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_CYCLE_WAIT (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_CYCLE_INDEX (2 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_CYCLE_STOP (4 << 25)</span><br><span> #define GMBUS_BYTE_COUNT_SHIFT 16</span><br><span> #define GMBUS_SLAVE_INDEX_SHIFT 8</span><br><span> #define GMBUS_SLAVE_ADDR_SHIFT 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_SLAVE_READ (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_SLAVE_WRITE (0<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_SLAVE_READ (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_SLAVE_WRITE (0 << 0)</span><br><span> #define GMBUS2 0x5108 /* status */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_INUSE (1<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_HW_WAIT_PHASE (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_STALL_TIMEOUT (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_INT (1<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_HW_RDY (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_SATOER (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_ACTIVE (1<<9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_INUSE (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_HW_WAIT_PHASE (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_STALL_TIMEOUT (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_INT (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_HW_RDY (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_SATOER (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_ACTIVE (1 << 9)</span><br><span> #define GMBUS3 0x510c /* data buffer bytes 3-0 */</span><br><span> #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_NAK_EN (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_IDLE_EN (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_HW_WAIT_EN (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_HW_RDY_EN (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_NAK_EN (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_IDLE_EN (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_HW_WAIT_EN (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_HW_RDY_EN (1 << 0)</span><br><span> #define GMBUS5 0x5120 /* byte index */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMBUS_2BYTE_INDEX_EN (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GMBUS_2BYTE_INDEX_EN (1UL << 31)</span><br><span> </span><br><span> /*</span><br><span> * Clock control & power management</span><br><span>@@ -942,23 +942,23 @@</span><br><span> #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */</span><br><span> #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */</span><br><span> #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPLL_LOCK_VLV (1<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPLL_LOCK_VLV (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPLL_INTEGRATED_CLOCK_VLV (1 << 13)</span><br><span> </span><br><span> #define SRX_INDEX 0x3c4</span><br><span> #define SRX_DATA 0x3c5</span><br><span> #define SR01 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define SR01_SCREEN_OFF (1<<5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SR01_SCREEN_OFF (1 << 5)</span><br><span> </span><br><span> #define PPCR 0x61204</span><br><span style="color: hsl(0, 100%, 40%);">-#define PPCR_ON (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PPCR_ON (1 << 0)</span><br><span> </span><br><span> #define DVOB 0x61140</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVOB_ON (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVOB_ON (1UL << 31)</span><br><span> #define DVOC 0x61160</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVOC_ON (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVOC_ON (1UL << 31)</span><br><span> #define LVDS 0x61180</span><br><span style="color: hsl(0, 100%, 40%);">-#define LVDS_ON (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LVDS_ON (1UL << 31)</span><br><span> #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)</span><br><span> #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)</span><br><span> #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)</span><br><span>@@ -1071,10 +1071,10 @@</span><br><span> #define DPLLA_TEST_M_BYPASS (1 << 2)</span><br><span> #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)</span><br><span> #define D_STATE 0x6104</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSTATE_GFX_RESET_I830 (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSTATE_PLL_D3_OFF (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSTATE_GFX_CLOCK_GATING (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSTATE_DOT_CLOCK_GATING (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSTATE_GFX_RESET_I830 (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSTATE_PLL_D3_OFF (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSTATE_GFX_CLOCK_GATING (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSTATE_DOT_CLOCK_GATING (1 << 0)</span><br><span> #define DSPCLK_GATE_D 0x6200</span><br><span> # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */</span><br><span> # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */</span><br><span>@@ -1186,7 +1186,7 @@</span><br><span> #define DEUC 0x6214 /* CRL only */</span><br><span> </span><br><span> #define FW_BLC_SELF_VLV 0x6500</span><br><span style="color: hsl(0, 100%, 40%);">-#define FW_CSPWRDWNEN (1<<15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FW_CSPWRDWNEN (1 << 15)</span><br><span> </span><br><span> /*</span><br><span> * Palette regs</span><br><span>@@ -1212,7 +1212,7 @@</span><br><span> * Logical Context regs</span><br><span> */</span><br><span> #define CCID 0x2180</span><br><span style="color: hsl(0, 100%, 40%);">-#define CCID_EN (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CCID_EN (1 << 0)</span><br><span> #define CXT_SIZE 0x21a0</span><br><span> #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)</span><br><span> #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)</span><br><span>@@ -1252,7 +1252,7 @@</span><br><span> </span><br><span> #define OVADD 0x30000</span><br><span> #define DOVSTA 0x30008</span><br><span style="color: hsl(0, 100%, 40%);">-#define OC_BUF (0x3<<20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define OC_BUF (0x3 << 20)</span><br><span> #define OGAMC5 0x30010</span><br><span> #define OGAMC4 0x30014</span><br><span> #define OGAMC3 0x30018</span><br><span>@@ -1301,47 +1301,47 @@</span><br><span> #define PCH_ADPA 0xe1100</span><br><span> #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_DAC_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_DAC_ENABLE (1UL << 31)</span><br><span> #define ADPA_DAC_DISABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_PIPE_SELECT_MASK (1<<30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_PIPE_SELECT_MASK (1 << 30)</span><br><span> #define ADPA_PIPE_A_SELECT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_PIPE_B_SELECT (1<<30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_PIPE_B_SELECT (1 << 30)</span><br><span> #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)</span><br><span> /* CPT uses bits 29:30 for pch transcoder select */</span><br><span> #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_USE_VGA_HVPOLARITY (1<<15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_USE_VGA_HVPOLARITY (1 << 15)</span><br><span> #define ADPA_SETS_HVPOLARITY 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_VSYNC_CNTL_DISABLE (1<<11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_VSYNC_CNTL_DISABLE (1 << 11)</span><br><span> #define ADPA_VSYNC_CNTL_ENABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_HSYNC_CNTL_DISABLE (1<<10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_HSYNC_CNTL_DISABLE (1 << 10)</span><br><span> #define ADPA_HSYNC_CNTL_ENABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)</span><br><span> #define ADPA_VSYNC_ACTIVE_LOW 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)</span><br><span> #define ADPA_HSYNC_ACTIVE_LOW 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_DPMS_MASK (~(3<<10))</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_DPMS_ON (0<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_DPMS_SUSPEND (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_DPMS_STANDBY (2<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ADPA_DPMS_OFF (3<<10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_DPMS_MASK (~(3 << 10))</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_DPMS_ON (0 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_DPMS_SUSPEND (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_DPMS_STANDBY (2 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ADPA_DPMS_OFF (3 << 10)</span><br><span> </span><br><span> </span><br><span> /* Hotplug control (945+ only) */</span><br><span>@@ -1466,7 +1466,7 @@</span><br><span> #define DVO_BLANK_ACTIVE_HIGH (1 << 2)</span><br><span> #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */</span><br><span> #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVO_PRESERVE_MASK (0x7<<24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVO_PRESERVE_MASK (0x7 << 24)</span><br><span> #define DVOA_SRCDIM 0x61124</span><br><span> #define DVOB_SRCDIM 0x61144</span><br><span> #define DVOC_SRCDIM 0x61164</span><br><span>@@ -1672,29 +1672,29 @@</span><br><span> /* New registers for PCH-split platforms. Safe where new bits show up, the</span><br><span> * register layout machtes with gen4 BLC_PWM_CTL[12]. */</span><br><span> #define BLC_PWM_CPU_CTL2 0x48250</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLC_PWM2_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLC_PWM2_ENABLE (1UL << 31)</span><br><span> #define BLC_PWM_CPU_CTL 0x48254</span><br><span> </span><br><span> #define BLM_HIST_CTL 0x48260</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_HIST_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_MODIF_TBL_ENABLE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_PIPE_A_SELECT (0<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_PIPE_B_SELECT (1<<29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_HIST_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_MODIF_TBL_ENABLE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_PIPE_A_SELECT (0 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_PIPE_B_SELECT (1 << 29)</span><br><span> #define ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HIST_MODE_YUV (0<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HIST_MODE_HSV (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_MODE_DIRECT (0<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_MODE_ADDITIVE (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENH_MODE_MULTIPLICATIVE (2<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BIN_REGISTER_SET (1<<11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HIST_MODE_YUV (0 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HIST_MODE_HSV (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_MODE_DIRECT (0 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_MODE_ADDITIVE (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENH_MODE_MULTIPLICATIVE (2 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIN_REGISTER_SET (1 << 11)</span><br><span> #define ENH_NUM_BINS 32</span><br><span> </span><br><span> #define BLM_HIST_ENH 0x48264</span><br><span> </span><br><span> #define BLM_HIST_GUARD_BAND 0x48268</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLM_HIST_INTR_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLM_HIST_EVENT_STATUS (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLM_HIST_INTR_DELAY_MASK (0xFF<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLM_HIST_INTR_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLM_HIST_EVENT_STATUS (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLM_HIST_INTR_DELAY_MASK (0xFF << 22)</span><br><span> #define BLM_HIST_INTR_DELAY_SHIFT 22</span><br><span> </span><br><span> /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is</span><br><span>@@ -2380,17 +2380,17 @@</span><br><span> #define DSL_LINEMASK_GEN2 0x00000fff</span><br><span> #define DSL_LINEMASK_GEN3 0x00001fff</span><br><span> #define _PIPEACONF 0x70008</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_ENABLE (1UL << 31)</span><br><span> #define PIPECONF_DISABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_DOUBLE_WIDE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define I965_PIPECONF_ACTIVE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_DOUBLE_WIDE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I965_PIPECONF_ACTIVE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)</span><br><span> #define PIPECONF_SINGLE_WIDE 0</span><br><span> #define PIPECONF_PIPE_UNLOCKED 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_PIPE_LOCKED (1<<25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_PIPE_LOCKED (1 << 25)</span><br><span> #define PIPECONF_PALETTE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_GAMMA (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_FORCE_BORDER (1<<25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_GAMMA (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_FORCE_BORDER (1 << 25)</span><br><span> #define PIPECONF_INTERLACE_MASK (7 << 21)</span><br><span> #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)</span><br><span> /* Note that pre-gen3 does not support interlaced display directly. Panel</span><br><span>@@ -2407,55 +2407,55 @@</span><br><span> #define PIPECONF_INTERLACED_ILK (3 << 21)</span><br><span> #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */</span><br><span> #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_CXSR_DOWNCLOCK (1<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)</span><br><span> #define PIPECONF_BPP_MASK (0x000000e0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_BPP_8 (0<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_BPP_10 (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_BPP_6 (2<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_BPP_12 (3<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_DITHER_EN (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_BPP_8 (0 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_BPP_10 (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_BPP_6 (2 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_BPP_12 (3 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_DITHER_EN (1 << 4)</span><br><span> #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_DITHER_TYPE_SP (0<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_DITHER_TYPE_ST1 (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_DITHER_TYPE_ST2 (2<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPECONF_DITHER_TYPE_TEMP (3<<2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_DITHER_TYPE_SP (0 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)</span><br><span> #define _PIPEASTAT 0x70024</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CRC_ERROR_ENABLE (1UL<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CRC_DONE_ENABLE (1UL<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_DPST_EVENT_ENABLE (1UL<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_DPST_EVENT_STATUS (1UL<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CRC_ERROR_ENABLE (1UL << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CRC_DONE_ENABLE (1UL << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_DPST_EVENT_ENABLE (1UL << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_DPST_EVENT_STATUS (1UL << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)</span><br><span> #define PIPE_BPC_MASK (7 << 5) /* Ironlake */</span><br><span> #define PIPE_8BPC (0 << 5)</span><br><span> #define PIPE_10BPC (1 << 5)</span><br><span>@@ -2470,37 +2470,37 @@</span><br><span> #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)</span><br><span> </span><br><span> #define VLV_DPFLIPSTAT 0x70028</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEB_LINE_COMPARE_INT_EN (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEB_HLINE_INT_EN (1<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEB_VBLANK_INT_EN (1<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITED_FLIPDONE_INT_EN (1<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEC_FLIPDONE_INT_EN (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANEB_FLIPDONE_INT_EN (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEA_LINE_COMPARE_INT_EN (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEA_HLINE_INT_EN (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPEA_VBLANK_INT_EN (1<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEB_FLIPDONE_INT_EN (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEA_FLIPDONE_INT_EN (1<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANEA_FLIPDONE_INT_EN (1<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEB_LINE_COMPARE_INT_EN (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEB_HLINE_INT_EN (1 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEB_VBLANK_INT_EN (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITED_FLIPDONE_INT_EN (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEC_FLIPDONE_INT_EN (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANEB_FLIPDONE_INT_EN (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEA_LINE_COMPARE_INT_EN (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEA_HLINE_INT_EN (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPEA_VBLANK_INT_EN (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEB_FLIPDONE_INT_EN (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEA_FLIPDONE_INT_EN (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANEA_FLIPDONE_INT_EN (1 << 16)</span><br><span> </span><br><span> #define DPINVGTT 0x7002c /* VLV only */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CURSORB_INVALID_GTT_INT_EN (1<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CURSORA_INVALID_GTT_INT_EN (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITED_INVALID_GTT_INT_EN (1<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEC_INVALID_GTT_INT_EN (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANEB_INVALID_GTT_INT_EN (1<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEB_INVALID_GTT_INT_EN (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEA_INVALID_GTT_INT_EN (1<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANEA_INVALID_GTT_INT_EN (1<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CURSORB_INVALID_GTT_INT_EN (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CURSORA_INVALID_GTT_INT_EN (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITED_INVALID_GTT_INT_EN (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEC_INVALID_GTT_INT_EN (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANEB_INVALID_GTT_INT_EN (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEB_INVALID_GTT_INT_EN (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEA_INVALID_GTT_INT_EN (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANEA_INVALID_GTT_INT_EN (1 << 16)</span><br><span> #define DPINVGTT_EN_MASK 0xff0000</span><br><span style="color: hsl(0, 100%, 40%);">-#define CURSORB_INVALID_GTT_STATUS (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CURSORA_INVALID_GTT_STATUS (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITED_INVALID_GTT_STATUS (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEC_INVALID_GTT_STATUS (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANEB_INVALID_GTT_STATUS (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEB_INVALID_GTT_STATUS (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITEA_INVALID_GTT_STATUS (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLANEA_INVALID_GTT_STATUS (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CURSORB_INVALID_GTT_STATUS (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CURSORA_INVALID_GTT_STATUS (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITED_INVALID_GTT_STATUS (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEC_INVALID_GTT_STATUS (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANEB_INVALID_GTT_STATUS (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEB_INVALID_GTT_STATUS (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITEA_INVALID_GTT_STATUS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLANEA_INVALID_GTT_STATUS (1 << 0)</span><br><span> #define DPINVGTT_STATUS_MASK 0xff</span><br><span> </span><br><span> #define DSPARB 0x70030</span><br><span>@@ -2513,40 +2513,40 @@</span><br><span> </span><br><span> #define DSPFW1 0x70034</span><br><span> #define DSPFW_SR_SHIFT 23</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSPFW_SR_MASK (0x1ff<<23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSPFW_SR_MASK (0x1ff << 23)</span><br><span> #define DSPFW_CURSORB_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSPFW_CURSORB_MASK (0x3f<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSPFW_CURSORB_MASK (0x3f << 16)</span><br><span> #define DSPFW_PLANEB_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSPFW_PLANEB_MASK (0x7f<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSPFW_PLANEB_MASK (0x7f << 8)</span><br><span> #define DSPFW_PLANEA_MASK (0x7f)</span><br><span> #define DSPFW2 0x70038</span><br><span> #define DSPFW_CURSORA_MASK 0x00003f00</span><br><span> #define DSPFW_CURSORA_SHIFT 8</span><br><span> #define DSPFW_PLANEC_MASK (0x7f)</span><br><span> #define DSPFW3 0x7003c</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSPFW_HPLL_SR_EN (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSPFW_HPLL_SR_EN (1UL << 31)</span><br><span> #define DSPFW_CURSOR_SR_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define PINEVIEW_SELF_REFRESH_EN (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSPFW_CURSOR_SR_MASK (0x3f<<24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PINEVIEW_SELF_REFRESH_EN (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSPFW_CURSOR_SR_MASK (0x3f << 24)</span><br><span> #define DSPFW_HPLL_CURSOR_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)</span><br><span> #define DSPFW_HPLL_SR_MASK (0x1ff)</span><br><span> </span><br><span> /* drain latency register values*/</span><br><span> #define DRAIN_LATENCY_PRECISION_32 32</span><br><span> #define DRAIN_LATENCY_PRECISION_16 16</span><br><span> #define VLV_DDL1 0x70050</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_CURSORA_PRECISION_32 (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_CURSORA_PRECISION_16 (0UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_CURSORA_PRECISION_32 (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_CURSORA_PRECISION_16 (0UL << 31)</span><br><span> #define DDL_CURSORA_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_PLANEA_PRECISION_32 (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_PLANEA_PRECISION_16 (0<<7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_PLANEA_PRECISION_32 (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_PLANEA_PRECISION_16 (0 << 7)</span><br><span> #define VLV_DDL2 0x70054</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_CURSORB_PRECISION_32 (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_CURSORB_PRECISION_16 (0UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_CURSORB_PRECISION_32 (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_CURSORB_PRECISION_16 (0UL << 31)</span><br><span> #define DDL_CURSORB_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_PLANEB_PRECISION_32 (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDL_PLANEB_PRECISION_16 (0<<7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_PLANEB_PRECISION_32 (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDL_PLANEB_PRECISION_16 (0 << 7)</span><br><span> </span><br><span> /* FIFO watermark sizes etc */</span><br><span> #define G4X_FIFO_LINE_SIZE 64</span><br><span>@@ -2583,31 +2583,31 @@</span><br><span> </span><br><span> /* define the Watermark register on Ironlake */</span><br><span> #define WM0_PIPEA_ILK 0x45100</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM0_PIPE_PLANE_MASK (0x7f<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM0_PIPE_PLANE_MASK (0x7f << 16)</span><br><span> #define WM0_PIPE_PLANE_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM0_PIPE_SPRITE_MASK (0x3f<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM0_PIPE_SPRITE_MASK (0x3f << 8)</span><br><span> #define WM0_PIPE_SPRITE_SHIFT 8</span><br><span> #define WM0_PIPE_CURSOR_MASK (0x1f)</span><br><span> </span><br><span> #define WM0_PIPEB_ILK 0x45104</span><br><span> #define WM0_PIPEC_IVB 0x45200</span><br><span> #define WM1_LP_ILK 0x45108</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM1_LP_SR_EN (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM1_LP_SR_EN (1UL << 31)</span><br><span> #define WM1_LP_LATENCY_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM1_LP_LATENCY_MASK (0x7f<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM1_LP_FBC_MASK (0xf<<20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM1_LP_LATENCY_MASK (0x7f << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM1_LP_FBC_MASK (0xf << 20)</span><br><span> #define WM1_LP_FBC_SHIFT 20</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM1_LP_SR_MASK (0x1ff<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM1_LP_SR_MASK (0x1ff << 8)</span><br><span> #define WM1_LP_SR_SHIFT 8</span><br><span> #define WM1_LP_CURSOR_MASK (0x3f)</span><br><span> #define WM2_LP_ILK 0x4510c</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM2_LP_EN (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM2_LP_EN (1UL << 31)</span><br><span> #define WM3_LP_ILK 0x45110</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM3_LP_EN (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM3_LP_EN (1UL << 31)</span><br><span> #define WM1S_LP_ILK 0x45120</span><br><span> #define WM2S_LP_IVB 0x45124</span><br><span> #define WM3S_LP_IVB 0x45128</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM1S_LP_EN (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM1S_LP_EN (1UL << 31)</span><br><span> </span><br><span> /* Memory latency timer register */</span><br><span> #define MLTR_ILK 0x11222</span><br><span>@@ -2730,38 +2730,38 @@</span><br><span> </span><br><span> /* Display A control */</span><br><span> #define _DSPACNTR 0x70180</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPLAY_PLANE_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPLAY_PLANE_ENABLE (1UL << 31)</span><br><span> #define DISPLAY_PLANE_DISABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_GAMMA_ENABLE (1<<30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_GAMMA_ENABLE (1 << 30)</span><br><span> #define DISPPLANE_GAMMA_DISABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_YUV422 (0x0<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_8BPP (0x2<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_BGRA555 (0x3<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_BGRX555 (0x4<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_BGRX565 (0x5<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_BGRX888 (0x6<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_BGRA888 (0x7<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_RGBX101010 (0x8<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_RGBA101010 (0x9<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_BGRX101010 (0xa<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_RGBX161616 (0xc<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_RGBX888 (0xe<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_RGBA888 (0xf<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_STEREO_ENABLE (1<<25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_YUV422 (0x0 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_8BPP (0x2 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_BGRA555 (0x3 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_BGRX555 (0x4 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_BGRX565 (0x5 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_BGRX888 (0x6 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_BGRA888 (0x7 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_RGBX101010 (0x8 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_RGBA101010 (0x9 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_BGRX101010 (0xa << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_RGBX161616 (0xc << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_RGBX888 (0xe << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_RGBA888 (0xf << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_STEREO_ENABLE (1 << 25)</span><br><span> #define DISPPLANE_STEREO_DISABLE 0</span><br><span> #define DISPPLANE_SEL_PIPE_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)</span><br><span> #define DISPPLANE_SEL_PIPE_A 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_SRC_KEY_ENABLE (1<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_SEL_PIPE_B (1 << DISPPLANE_SEL_PIPE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)</span><br><span> #define DISPPLANE_SRC_KEY_DISABLE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_LINE_DOUBLE (1<<20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_LINE_DOUBLE (1 << 20)</span><br><span> #define DISPPLANE_NO_LINE_DOUBLE 0</span><br><span> #define DISPPLANE_STEREO_POLARITY_FIRST 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_TILED (1<<10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_TILED (1 << 10)</span><br><span> #define _DSPAADDR 0x70184</span><br><span> #define _DSPASTRIDE 0x70188</span><br><span> #define _DSPAPOS 0x7018C /* reserved */</span><br><span>@@ -2809,20 +2809,20 @@</span><br><span> #define _PIPEBCONF 0x71008</span><br><span> #define _PIPEBSTAT 0x71024</span><br><span> #define _PIPEBFRAMEHIGH 0x71040</span><br><span style="color: hsl(0, 100%, 40%);">-#define _PIPEBFRAMEPIXEL 0x71044</span><br><span style="color: hsl(120, 100%, 40%);">+#define _PIPEBFRAMEPIXEL 0x71044</span><br><span> #define _PIPEB_FRMCOUNT_GM45 0x71040</span><br><span> #define _PIPEB_FLIPCOUNT_GM45 0x71044</span><br><span> </span><br><span> </span><br><span> /* Display B control */</span><br><span> #define _DSPBCNTR 0x71180</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)</span><br><span> #define DISPPLANE_ALPHA_TRANS_DISABLE 0</span><br><span> #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0</span><br><span> #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)</span><br><span> #define _DSPBADDR 0x71184</span><br><span> #define _DSPBSTRIDE 0x71188</span><br><span style="color: hsl(0, 100%, 40%);">-#define _DSPBPOS 0x7118C</span><br><span style="color: hsl(120, 100%, 40%);">+#define _DSPBPOS 0x7118C</span><br><span> #define _DSPBSIZE 0x71190</span><br><span> #define _DSPBSURF 0x7119C</span><br><span> #define _DSPBTILEOFF 0x711A4</span><br><span>@@ -2831,23 +2831,23 @@</span><br><span> </span><br><span> /* Sprite A control */</span><br><span> #define _DVSACNTR 0x72180</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_GAMMA_ENABLE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_PIXFORMAT_MASK (3<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FORMAT_YUV422 (0<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FORMAT_RGBX101010 (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FORMAT_RGBX888 (2<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FORMAT_RGBX161616 (3<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_SOURCE_KEY (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_RGB_ORDER_XBGR (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_YUV_BYTE_ORDER_MASK (3<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_YUV_ORDER_YUYV (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_YUV_ORDER_UYVY (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_YUV_ORDER_YVYU (2<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_YUV_ORDER_VYUY (3<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_DEST_KEY (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_TRICKLE_FEED_DISABLE (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_TILED (1<<10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_GAMMA_ENABLE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_PIXFORMAT_MASK (3 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FORMAT_YUV422 (0 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FORMAT_RGBX101010 (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FORMAT_RGBX888 (2 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FORMAT_RGBX161616 (3 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_SOURCE_KEY (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_RGB_ORDER_XBGR (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_YUV_ORDER_YUYV (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_YUV_ORDER_UYVY (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_YUV_ORDER_YVYU (2 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_YUV_ORDER_VYUY (3 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_DEST_KEY (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_TRICKLE_FEED_DISABLE (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_TILED (1 << 10)</span><br><span> #define _DVSALINOFF 0x72184</span><br><span> #define _DVSASTRIDE 0x72188</span><br><span> #define _DVSAPOS 0x7218c</span><br><span>@@ -2859,13 +2859,13 @@</span><br><span> #define _DVSATILEOFF 0x721a4</span><br><span> #define _DVSASURFLIVE 0x721ac</span><br><span> #define _DVSASCALE 0x72204</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_SCALE_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FILTER_MASK (3<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FILTER_MEDIUM (0<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FILTER_ENHANCING (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_FILTER_SOFTENING (2<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_SCALE_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FILTER_MASK (3 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FILTER_MEDIUM (0 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FILTER_ENHANCING (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_FILTER_SOFTENING (2 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)</span><br><span> #define _DVSAGAMC 0x72300</span><br><span> </span><br><span> #define _DVSBCNTR 0x73180</span><br><span>@@ -2896,29 +2896,29 @@</span><br><span> #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)</span><br><span> </span><br><span> #define _SPRA_CTL 0x70280</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_GAMMA_ENABLE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_PIXFORMAT_MASK (7<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FORMAT_YUV422 (0<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FORMAT_RGBX101010 (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FORMAT_RGBX888 (2<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FORMAT_RGBX161616 (3<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FORMAT_YUV444 (4<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_CSC_ENABLE (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_SOURCE_KEY (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_ORDER_YUYV (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_ORDER_UYVY (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_ORDER_YVYU (2<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_YUV_ORDER_VYUY (3<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_INT_GAMMA_ENABLE (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_TILED (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_DEST_KEY (1<<2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_GAMMA_ENABLE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_PIXFORMAT_MASK (7 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FORMAT_YUV422 (0 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FORMAT_RGBX101010 (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FORMAT_RGBX888 (2 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FORMAT_RGBX161616 (3 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FORMAT_YUV444 (4 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_CSC_ENABLE (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_SOURCE_KEY (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_ORDER_YUYV (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_ORDER_UYVY (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_ORDER_YVYU (2 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_YUV_ORDER_VYUY (3 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_INT_GAMMA_ENABLE (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_TILED (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_DEST_KEY (1 << 2)</span><br><span> #define _SPRA_LINOFF 0x70284</span><br><span> #define _SPRA_STRIDE 0x70288</span><br><span> #define _SPRA_POS 0x7028c</span><br><span>@@ -2931,13 +2931,13 @@</span><br><span> #define _SPRA_OFFSET 0x702a4</span><br><span> #define _SPRA_SURFLIVE 0x702ac</span><br><span> #define _SPRA_SCALE 0x70304</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_SCALE_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FILTER_MASK (3<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FILTER_MEDIUM (0<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FILTER_ENHANCING (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_FILTER_SOFTENING (2<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_SCALE_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FILTER_MASK (3 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FILTER_MEDIUM (0 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FILTER_ENHANCING (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_FILTER_SOFTENING (2 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)</span><br><span> #define _SPRA_GAMC 0x70400</span><br><span> </span><br><span> #define _SPRB_CTL 0x71280</span><br><span>@@ -2979,7 +2979,7 @@</span><br><span> /* Ironlake */</span><br><span> </span><br><span> #define CPU_VGACNTRL 0x41000</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_VGA_DISABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPU_VGA_DISABLE (1UL << 31)</span><br><span> </span><br><span> #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030</span><br><span> #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)</span><br><span>@@ -3012,7 +3012,7 @@</span><br><span> # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)</span><br><span> </span><br><span> #define FDI_PLL_FREQ_CTL 0x46030</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)</span><br><span> #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00</span><br><span> #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff</span><br><span> </span><br><span>@@ -3070,14 +3070,14 @@</span><br><span> /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */</span><br><span> #define _PFA_CTL_1 0x68080</span><br><span> #define _PFB_CTL_1 0x68880</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_PIPE_SEL_MASK_IVB (3<<29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_PIPE_SEL_MASK_IVB (3 << 29)</span><br><span> #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_FILTER_MASK (3<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_FILTER_PROGRAMMED (0<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_FILTER_MED_3x3 (1<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_FILTER_EDGE_ENHANCE (2<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PF_FILTER_EDGE_SOFTEN (3<<23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_FILTER_MASK (3 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_FILTER_PROGRAMMED (0 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_FILTER_MED_3x3 (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_FILTER_EDGE_ENHANCE (2 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PF_FILTER_EDGE_SOFTEN (3 << 23)</span><br><span> #define _PFA_WIN_SZ 0x68074</span><br><span> #define _PFB_WIN_SZ 0x68874</span><br><span> #define _PFA_WIN_POS 0x68070</span><br><span>@@ -3126,23 +3126,23 @@</span><br><span> #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)</span><br><span> </span><br><span> /* More Ivybridge lolz */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_ERR_DEBUG_IVB (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_GSE_IVB (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PCH_EVENT_IVB (1<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_DP_A_HOTPLUG_IVB (1<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_AUX_CHANNEL_A_IVB (1<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PLANEC_FLIP_DONE_IVB (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PIPEC_VBLANK_IVB (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PLANEB_FLIP_DONE_IVB (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PIPEB_VBLANK_IVB (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PLANEA_FLIP_DONE_IVB (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DE_PIPEA_VBLANK_IVB (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_ERR_DEBUG_IVB (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_GSE_IVB (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PCH_EVENT_IVB (1 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_DP_A_HOTPLUG_IVB (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_AUX_CHANNEL_A_IVB (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PIPEC_VBLANK_IVB (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PIPEB_VBLANK_IVB (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DE_PIPEA_VBLANK_IVB (1 << 0)</span><br><span> </span><br><span> #define VLV_MASTER_IER 0x4400c /* Gunit master IER */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MASTER_INTERRUPT_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASTER_INTERRUPT_ENABLE (1UL << 31)</span><br><span> </span><br><span> #define DEISR 0x44000</span><br><span> #define DEIMR 0x44004</span><br><span>@@ -3172,15 +3172,15 @@</span><br><span> #define ILK_DISPLAY_CHICKEN2 0x42004</span><br><span> /* Required on all Ironlake and Sandybridge according to the B-Spec. */</span><br><span> #define ILK_ELPIN_409_SELECT (1 << 25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_DPARB_GATE (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_VSDPFD_FULL (1<<21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_DPARB_GATE (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_VSDPFD_FULL (1 << 21)</span><br><span> #define ILK_DISPLAY_CHICKEN_FUSES 0x42014</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_INTERNAL_GRAPHICS_DISABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_HDCP_DISABLE (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_eDP_A_DISABLE (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ILK_DESKTOP (1<<23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_INTERNAL_GRAPHICS_DISABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_HDCP_DISABLE (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_eDP_A_DISABLE (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ILK_DESKTOP (1 << 23)</span><br><span> </span><br><span> #define ILK_DSPCLK_GATE_D 0x42020</span><br><span> #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)</span><br><span>@@ -3194,26 +3194,26 @@</span><br><span> # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)</span><br><span> </span><br><span> #define DISP_ARB_CTL 0x45000</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISP_TILE_SURFACE_SWIZZLING (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISP_FBC_WM_DIS (1<<15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISP_TILE_SURFACE_SWIZZLING (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISP_FBC_WM_DIS (1 << 15)</span><br><span> </span><br><span> /* GEN7 chicken */</span><br><span> #define GEN7_COMMON_SLICE_CHICKEN1 0x7010</span><br><span style="color: hsl(0, 100%, 40%);">-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))</span><br><span style="color: hsl(120, 100%, 40%);">+# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))</span><br><span> </span><br><span> #define GEN7_L3CNTLREG1 0xB01C</span><br><span> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_L3AGDIS (1<<19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_L3AGDIS (1 << 19)</span><br><span> </span><br><span> #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030</span><br><span> #define GEN7_WA_L3_CHICKEN_MODE 0x20000000</span><br><span> </span><br><span> #define GEN7_L3SQCREG4 0xb034</span><br><span style="color: hsl(0, 100%, 40%);">-#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)</span><br><span> </span><br><span> /* WaCatErrorRejectionIssue */</span><br><span> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)</span><br><span> </span><br><span> #define HSW_FUSE_STRAP 0x42014</span><br><span> #define HSW_CDCLK_LIMIT (1 << 24)</span><br><span>@@ -3349,7 +3349,7 @@</span><br><span> #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)</span><br><span> </span><br><span> #define _PCH_FPA0 0xc6040</span><br><span style="color: hsl(0, 100%, 40%);">-#define FP_CB_TUNE (0x3<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FP_CB_TUNE (0x3 << 22)</span><br><span> #define _PCH_FPA1 0xc6044</span><br><span> #define _PCH_FPB0 0xc6048</span><br><span> #define _PCH_FPB1 0xc604c</span><br><span>@@ -3360,32 +3360,32 @@</span><br><span> </span><br><span> #define PCH_DREF_CONTROL 0xC6200</span><br><span> #define DREF_CONTROL_MASK 0x7fc3</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC_SOURCE_DISABLE (0<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC_SOURCE_ENABLE (2<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC_SOURCE_MASK (3<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_NONSPREAD_CK505_ENABLE (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_NONSPREAD_SOURCE_MASK (3<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC4_DOWNSPREAD (0<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC4_CENTERSPREAD (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC1_DISABLE (0<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DREF_SSC1_ENABLE (1<<1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC_SOURCE_DISABLE (0 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC_SOURCE_ENABLE (2 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC_SOURCE_MASK (3 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC4_DOWNSPREAD (0 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC4_CENTERSPREAD (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC1_DISABLE (0 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DREF_SSC1_ENABLE (1 << 1)</span><br><span> #define DREF_SSC4_DISABLE (0)</span><br><span> #define DREF_SSC4_ENABLE (1)</span><br><span> </span><br><span> #define PCH_RAWCLK_FREQ 0xc6204</span><br><span> #define FDL_TP1_TIMER_SHIFT 12</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDL_TP1_TIMER_MASK (3<<12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDL_TP1_TIMER_MASK (3 << 12)</span><br><span> #define FDL_TP2_TIMER_SHIFT 10</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDL_TP2_TIMER_MASK (3<<10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDL_TP2_TIMER_MASK (3 << 10)</span><br><span> #define RAWCLK_FREQ_MASK 0x3ff</span><br><span> </span><br><span> #define PCH_DPLL_TMR_CFG 0xc6208</span><br><span>@@ -3394,14 +3394,14 @@</span><br><span> #define PCH_SSC4_AUX_PARMS 0xc6214</span><br><span> </span><br><span> #define PCH_DPLL_SEL 0xc7000</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANSA_DPLL_ENABLE (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANSA_DPLLB_SEL (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANSA_DPLL_ENABLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANSA_DPLLB_SEL (1 << 0)</span><br><span> #define TRANSA_DPLLA_SEL 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANSB_DPLL_ENABLE (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANSB_DPLLB_SEL (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANSB_DPLL_ENABLE (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANSB_DPLLB_SEL (1 << 4)</span><br><span> #define TRANSB_DPLLA_SEL (0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANSC_DPLL_ENABLE (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANSC_DPLLB_SEL (1<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANSC_DPLL_ENABLE (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANSC_DPLLB_SEL (1 << 8)</span><br><span> #define TRANSC_DPLLA_SEL (0)</span><br><span> </span><br><span> /* transcoder */</span><br><span>@@ -3541,34 +3541,34 @@</span><br><span> #define _PCH_TRANSACONF 0xf0008</span><br><span> #define _PCH_TRANSBCONF 0xf1008</span><br><span> #define PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DISABLE (0UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_STATE_MASK (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_STATE_DISABLE (0<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_STATE_ENABLE (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_FSYNC_DELAY_HB1 (0<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_FSYNC_DELAY_HB2 (1<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_FSYNC_DELAY_HB3 (2<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_FSYNC_DELAY_HB4 (3<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_AUDIO_ONLY (1<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_VIDEO_AUDIO (0<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_INTERLACE_MASK (7<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_PROGRESSIVE (0<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_INTERLACED (3<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_LEGACY_INTERLACED_ILK (2<<21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_8BPC (0<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_10BPC (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_6BPC (2<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_12BPC (3<<5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DISABLE (0UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_STATE_MASK (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_STATE_DISABLE (0 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_STATE_ENABLE (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_FSYNC_DELAY_HB1 (0 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_FSYNC_DELAY_HB2 (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_FSYNC_DELAY_HB3 (2 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_FSYNC_DELAY_HB4 (3 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_AUDIO_ONLY (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_VIDEO_AUDIO (0 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_INTERLACE_MASK (7 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_PROGRESSIVE (0 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_INTERLACED (3 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_8BPC (0 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_10BPC (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_6BPC (2 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_12BPC (3 << 5)</span><br><span> </span><br><span> #define _TRANSA_CHICKEN1 0xf0060</span><br><span> #define _TRANSB_CHICKEN1 0xf1060</span><br><span> #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)</span><br><span> #define _TRANSA_CHICKEN2 0xf0064</span><br><span> #define _TRANSB_CHICKEN2 0xf1064</span><br><span> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL << 31)</span><br><span> </span><br><span> </span><br><span> #define SOUTH_CHICKEN1 0xc2000</span><br><span>@@ -3578,114 +3578,114 @@</span><br><span> #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))</span><br><span> #define FDI_BC_BIFURCATION_SELECT (1 << 12)</span><br><span> #define SOUTH_CHICKEN2 0xc2004</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPLS_EDP_PPS_FIX_DIS (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPLS_EDP_PPS_FIX_DIS (1 << 0)</span><br><span> </span><br><span> #define _FDI_RXA_CHICKEN 0xc200c</span><br><span> #define _FDI_RXB_CHICKEN 0xc2010</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)</span><br><span> #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)</span><br><span> </span><br><span> #define SOUTH_DSPCLK_GATE_D 0xc2020</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)</span><br><span> </span><br><span> /* CPU: FDI_TX */</span><br><span> #define _FDI_TXA_CTL 0x60100</span><br><span> #define _FDI_TXB_CTL 0x61100</span><br><span> #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_TX_DISABLE (0UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_TX_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_NONE (3<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_TX_DISABLE (0UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_TX_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_NONE (3 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)</span><br><span> /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.</span><br><span> SNB has different settings. */</span><br><span> /* SNB A-stepping */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)</span><br><span> /* SNB B-stepping */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_DP_PORT_WIDTH_X1 (0<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_DP_PORT_WIDTH_X2 (1<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_DP_PORT_WIDTH_X3 (2<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_DP_PORT_WIDTH_X4 (3<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_DP_PORT_WIDTH_X1 (0 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_DP_PORT_WIDTH_X2 (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_DP_PORT_WIDTH_X3 (2 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_DP_PORT_WIDTH_X4 (3 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)</span><br><span> /* Ironlake: hardwired to 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_TX_PLL_ENABLE (1<<14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_TX_PLL_ENABLE (1 << 14)</span><br><span> </span><br><span> /* Ivybridge has different bits for lolz */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_NONE_IVB (3<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)</span><br><span> </span><br><span> /* both Tx and Rx */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_COMPOSITE_SYNC (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_AUTO (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_SCRAMBLING_ENABLE (0<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_SCRAMBLING_DISABLE (1<<7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_COMPOSITE_SYNC (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_AUTO (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_SCRAMBLING_ENABLE (0 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_SCRAMBLING_DISABLE (1 << 7)</span><br><span> </span><br><span> /* FDI_RX, FDI_X is hard-wired to Transcoder_X */</span><br><span> #define _FDI_RXA_CTL 0xf000c</span><br><span> #define _FDI_RXB_CTL 0xf100c</span><br><span> #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_ENABLE (1UL << 31)</span><br><span> /* train, dp width same as FDI_TX */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_FS_ERRC_ENABLE (1<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_FE_ERRC_ENABLE (1<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_DP_PORT_WIDTH_X8 (7<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_8BPC (0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_10BPC (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_6BPC (2<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_12BPC (3<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_REVERSE_OVERWRITE (1<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_DMI_LINK_REVERSE_MASK (1<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_PLL_ENABLE (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_FS_ERR_REPORT_ENABLE (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_FE_ERR_REPORT_ENABLE (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_PCDCLK (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_FS_ERRC_ENABLE (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_FE_ERRC_ENABLE (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_DP_PORT_WIDTH_X8 (7 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_8BPC (0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_10BPC (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_6BPC (2 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_12BPC (3 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_REVERSE_OVERWRITE (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_DMI_LINK_REVERSE_MASK (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_PLL_ENABLE (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_FS_ERR_REPORT_ENABLE (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_FE_ERR_REPORT_ENABLE (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_PCDCLK (1 << 4)</span><br><span> /* CPT */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_AUTO_TRAINING (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_AUTO_TRAINING (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)</span><br><span> /* LPT */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_PORT_WIDTH_2X_LPT (1<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_PORT_WIDTH_1X_LPT (0<<19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_PORT_WIDTH_2X_LPT (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_PORT_WIDTH_1X_LPT (0 << 19)</span><br><span> </span><br><span> #define _FDI_RXA_MISC 0xf0010</span><br><span> #define _FDI_RXB_MISC 0xf1010</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_PWRDN_LANE1_MASK (3<<26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_PWRDN_LANE1_MASK (3 << 26)</span><br><span> #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_PWRDN_LANE0_MASK (3<<24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_PWRDN_LANE0_MASK (3 << 24)</span><br><span> #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_TP1_TO_TP2_48 (2<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_TP1_TO_TP2_64 (3<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_FDI_DELAY_90 (0x90<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_TP1_TO_TP2_48 (2 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_TP1_TO_TP2_64 (3 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_FDI_DELAY_90 (0x90 << 0)</span><br><span> #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)</span><br><span> </span><br><span> #define _FDI_RXA_TUSIZE1 0xf0030</span><br><span>@@ -3696,17 +3696,17 @@</span><br><span> #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)</span><br><span> </span><br><span> /* FDI_RX interrupt register format */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_INTER_LANE_ALIGN (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_FS_CODE_ERR (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_FE_CODE_ERR (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_HDCP_LINK_FAIL (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_INTER_LANE_ALIGN (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_FS_CODE_ERR (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_FE_CODE_ERR (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_HDCP_LINK_FAIL (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)</span><br><span> </span><br><span> #define _FDI_RXA_IIR 0xf0014</span><br><span> #define _FDI_RXA_IMR 0xf0018</span><br><span>@@ -3831,49 +3831,49 @@</span><br><span> </span><br><span> /* CPT */</span><br><span> #define PORT_TRANS_A_SEL_CPT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_TRANS_B_SEL_CPT (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_TRANS_C_SEL_CPT (2<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_TRANS_SEL_MASK (3<<29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_TRANS_B_SEL_CPT (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_TRANS_C_SEL_CPT (2 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_TRANS_SEL_MASK (3 << 29)</span><br><span> #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_TO_PIPE(val) (((val) & (1 << 30)) >> 30)</span><br><span> #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)</span><br><span> </span><br><span> #define TRANS_DP_CTL_A 0xe0300</span><br><span> #define TRANS_DP_CTL_B 0xe1300</span><br><span> #define TRANS_DP_CTL_C 0xe2300</span><br><span> #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_OUTPUT_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_PORT_SEL_B (0<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_PORT_SEL_C (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_PORT_SEL_D (2<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_PORT_SEL_NONE (3<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_PORT_SEL_MASK (3<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_AUDIO_ONLY (1<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_ENH_FRAMING (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_8BPC (0<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_10BPC (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_6BPC (2<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_12BPC (3<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_BPC_MASK (3<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_OUTPUT_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_PORT_SEL_B (0 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_PORT_SEL_C (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_PORT_SEL_D (2 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_PORT_SEL_NONE (3 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_PORT_SEL_MASK (3 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_AUDIO_ONLY (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_ENH_FRAMING (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_8BPC (0 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_10BPC (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_6BPC (2 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_12BPC (3 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_BPC_MASK (3 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)</span><br><span> #define TRANS_DP_VSYNC_ACTIVE_LOW 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)</span><br><span> #define TRANS_DP_HSYNC_ACTIVE_LOW 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DP_SYNC_MASK (3<<3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DP_SYNC_MASK (3 << 3)</span><br><span> </span><br><span> /* SNB eDP training params */</span><br><span> /* SNB A-stepping */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)</span><br><span> /* SNB B-stepping */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)</span><br><span> </span><br><span> /* IVB */</span><br><span> #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)</span><br><span>@@ -3891,7 +3891,7 @@</span><br><span> #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)</span><br><span> #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)</span><br><span> </span><br><span> #define FORCEWAKE 0xA18C</span><br><span> #define FORCEWAKE_VLV 0x1300b0</span><br><span>@@ -3903,13 +3903,13 @@</span><br><span> #define FORCEWAKE_USER 0x2</span><br><span> #define FORCEWAKE_MT_ACK 0x130040</span><br><span> #define ECOBUS 0xa180</span><br><span style="color: hsl(0, 100%, 40%);">-#define FORCEWAKE_MT_ENABLE (1<<5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FORCEWAKE_MT_ENABLE (1 << 5)</span><br><span> </span><br><span> #define GTFIFODBG 0x120000</span><br><span> #define GT_FIFO_CPU_ERROR_MASK 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define GT_FIFO_OVFERR (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GT_FIFO_IAWRERR (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GT_FIFO_IARDERR (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GT_FIFO_OVFERR (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GT_FIFO_IAWRERR (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GT_FIFO_IARDERR (1 << 0)</span><br><span> </span><br><span> #define GT_FIFO_FREE_ENTRIES 0x120008</span><br><span> #define GT_FIFO_NUM_RESERVED_ENTRIES 20</span><br><span>@@ -3926,41 +3926,41 @@</span><br><span> # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)</span><br><span> </span><br><span> #define GEN7_UCGCTL4 0x940c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)</span><br><span> </span><br><span> #define GEN6_RPNSWREQ 0xA008</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_TURBO_DISABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_TURBO_DISABLE (1UL << 31)</span><br><span> #define GEN6_FREQUENCY(x) ((x)<<25)</span><br><span> #define GEN6_OFFSET(x) ((x)<<19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_AGGRESSIVE_TURBO (0<<15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_AGGRESSIVE_TURBO (0 << 15)</span><br><span> #define GEN6_RC_VIDEO_FREQ 0xA00C</span><br><span> #define GEN6_RC_CONTROL 0xA090</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RC_CTL_RC6_ENABLE (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RC_CTL_RC7_ENABLE (1<<22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)</span><br><span> #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RC_CTL_HW_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RC_CTL_HW_ENABLE (1UL << 31)</span><br><span> #define GEN6_RP_DOWN_TIMEOUT 0xA010</span><br><span> #define GEN6_RP_INTERRUPT_LIMITS 0xA014</span><br><span> #define GEN6_RPSTAT1 0xA01C</span><br><span> #define GEN6_CAGF_SHIFT 8</span><br><span> #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)</span><br><span> #define GEN6_RP_CONTROL 0xA024</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_TURBO (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_MODE_MASK (3<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_HW_MODE (1<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_SW_MODE (0<<9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_MEDIA_IS_GFX (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_ENABLE (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_UP_IDLE_MIN (0x1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_UP_BUSY_AVG (0x2<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_UP_BUSY_CONT (0x4<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_RP_DOWN_IDLE_AVG (0x2<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_TURBO (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_HW_MODE (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_SW_MODE (0 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_MEDIA_IS_GFX (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_ENABLE (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_RP_DOWN_IDLE_AVG (0x2 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)</span><br><span> #define GEN6_RP_UP_THRESHOLD 0xA02C</span><br><span> #define GEN6_RP_DOWN_THRESHOLD 0xA030</span><br><span> #define GEN6_RP_CUR_UP_EI 0xA050</span><br><span>@@ -3992,13 +3992,13 @@</span><br><span> #define GEN6_PMIMR 0x44024 /* rps_lock */</span><br><span> #define GEN6_PMIIR 0x44028</span><br><span> #define GEN6_PMIER 0x4402C</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_MBOX_EVENT (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_THERMAL_EVENT (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_RP_UP_THRESHOLD (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_MBOX_EVENT (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_THERMAL_EVENT (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)</span><br><span> #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \</span><br><span> GEN6_PM_RP_DOWN_THRESHOLD | \</span><br><span> GEN6_PM_RP_DOWN_TIMEOUT)</span><br><span>@@ -4009,7 +4009,7 @@</span><br><span> #define GEN6_GT_GFX_RC6pp 0x138110</span><br><span> </span><br><span> #define GEN6_PCODE_MAILBOX 0x138124</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_PCODE_READY (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_PCODE_READY (1UL << 31)</span><br><span> #define GEN6_READ_OC_PARAMS 0xc</span><br><span> #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8</span><br><span> #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9</span><br><span>@@ -4021,7 +4021,7 @@</span><br><span> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8</span><br><span> </span><br><span> #define GEN6_GT_CORE_STATUS 0x138060</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN6_CORE_CPD_STATE_MASK (7<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN6_CORE_CPD_STATE_MASK (7 << 4)</span><br><span> #define GEN6_RCn_MASK 7</span><br><span> #define GEN6_RC0 0</span><br><span> #define GEN6_RC3 2</span><br><span>@@ -4029,33 +4029,33 @@</span><br><span> #define GEN6_RC7 4</span><br><span> </span><br><span> #define GEN7_MISCCPCTL (0x9424)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)</span><br><span> </span><br><span> /* IVYBRIDGE DPF */</span><br><span> #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_PARITY_ERROR_VALID (1<<13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_L3CDERRST1_BANK_MASK (3<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_PARITY_ERROR_VALID (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)</span><br><span> #define GEN7_PARITY_ERROR_ROW(reg) \</span><br><span> ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)</span><br><span> #define GEN7_PARITY_ERROR_BANK(reg) \</span><br><span> ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)</span><br><span> #define GEN7_PARITY_ERROR_SUBBANK(reg) \</span><br><span> ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_L3CDERRST1_ENABLE (1<<7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_L3CDERRST1_ENABLE (1 << 7)</span><br><span> </span><br><span> #define GEN7_L3LOG_BASE 0xB070</span><br><span> #define GEN7_L3LOG_SIZE 0x80</span><br><span> </span><br><span> #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */</span><br><span> #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_MAX_PS_THREAD_DEP (8<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_MAX_PS_THREAD_DEP (8 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)</span><br><span> </span><br><span> #define GEN7_ROW_CHICKEN2 0xe4f4</span><br><span> #define GEN7_ROW_CHICKEN2_GT2 0xf4f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define DOP_CLOCK_GATING_DISABLE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DOP_CLOCK_GATING_DISABLE (1 << 0)</span><br><span> </span><br><span> #define G4X_AUD_VID_DID 0x62020</span><br><span> #define INTEL_AUDIO_DEVCL 0x808629FB</span><br><span>@@ -4159,30 +4159,30 @@</span><br><span> </span><br><span> #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */</span><br><span> #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_INACTIVE_C (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_INACTIVE_B (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_INACTIVE_A (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_OUTPUT_ENABLE_A (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_OUTPUT_ENABLE_B (1<<6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_OUTPUT_ENABLE_C (1<<10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_ELD_VALID_A (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_ELD_VALID_B (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_ELD_VALID_C (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_CP_READY_A (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_CP_READY_B (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AUDIO_CP_READY_C (1<<9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_INACTIVE_C (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_INACTIVE_B (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_INACTIVE_A (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_OUTPUT_ENABLE_A (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_OUTPUT_ENABLE_B (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_OUTPUT_ENABLE_C (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_ELD_VALID_A (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_ELD_VALID_B (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_ELD_VALID_C (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_CP_READY_A (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_CP_READY_B (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_CP_READY_C (1 << 9)</span><br><span> </span><br><span> /* HSW Power Wells */</span><br><span> #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */</span><br><span> #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */</span><br><span> #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */</span><br><span> #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HSW_PWR_WELL_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HSW_PWR_WELL_STATE (1<<30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HSW_PWR_WELL_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HSW_PWR_WELL_STATE (1 << 30)</span><br><span> #define HSW_PWR_WELL_CTL5 0x45410</span><br><span style="color: hsl(0, 100%, 40%);">-#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define HSW_PWR_WELL_FORCE_ON (1<<19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HSW_PWR_WELL_FORCE_ON (1 << 19)</span><br><span> #define HSW_PWR_WELL_CTL6 0x45414</span><br><span> </span><br><span> /* Per-pipe DDI Function Control */</span><br><span>@@ -4192,80 +4192,80 @@</span><br><span> #define TRANS_DDI_FUNC_CTL_EDP 0x6F400</span><br><span> #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \</span><br><span> TRANS_DDI_FUNC_CTL_B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_FUNC_ENABLE (1UL<<31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_FUNC_ENABLE (1UL << 31)</span><br><span> /* Those bits are ignored by pipe EDP since it can only connect to DDI A */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PORT_MASK (7<<28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PORT_MASK (7 << 28)</span><br><span> #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PORT_NONE (0<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_MODE_SELECT_MASK (7<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_MODE_SELECT_DVI (1<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_MODE_SELECT_FDI (4<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_BPC_MASK (7<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_BPC_8 (0<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_BPC_10 (1<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_BPC_6 (2<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_BPC_12 (3<<20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PVSYNC (1<<17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PHSYNC (1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_EDP_INPUT_MASK (7<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_BFI_ENABLE (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PORT_WIDTH_X1 (0<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PORT_WIDTH_X2 (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_DDI_PORT_WIDTH_X4 (3<<1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PORT_NONE (0 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_MODE_SELECT_FDI (4 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_BPC_MASK (7 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_BPC_8 (0 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_BPC_10 (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_BPC_6 (2 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_BPC_12 (3 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PVSYNC (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PHSYNC (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_BFI_ENABLE (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PORT_WIDTH_X1 (0 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PORT_WIDTH_X2 (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_DDI_PORT_WIDTH_X4 (3 << 1)</span><br><span> </span><br><span> /* DisplayPort Transport Control */</span><br><span> #define DP_TP_CTL_A 0x64040</span><br><span> #define DP_TP_CTL_B 0x64140</span><br><span> #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_MODE_SST (0<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_MODE_MST (1<<27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_MODE_SST (0 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_MODE_MST (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)</span><br><span> </span><br><span> /* DisplayPort Transport Status */</span><br><span> #define DP_TP_STATUS_A 0x64044</span><br><span> #define DP_TP_STATUS_B 0x64144</span><br><span> #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_STATUS_IDLE_DONE (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_STATUS_IDLE_DONE (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)</span><br><span> </span><br><span> /* DDI Buffer Control */</span><br><span> #define DDI_BUF_CTL_A 0x64000</span><br><span> #define DDI_BUF_CTL_B 0x64100</span><br><span> #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_CTL_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_EMP_MASK (0xf<<24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_BUF_IS_IDLE (1<<7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_A_4_LANES (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_CTL_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_400MV_0DB_HSW (0 << 24) /* Sel0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_400MV_3_5DB_HSW (1 << 24) /* Sel1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_400MV_6DB_HSW (2 << 24) /* Sel2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_400MV_9_5DB_HSW (3 << 24) /* Sel3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_600MV_0DB_HSW (4 << 24) /* Sel4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_600MV_3_5DB_HSW (5 << 24) /* Sel5 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_600MV_6DB_HSW (6 << 24) /* Sel6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_800MV_0DB_HSW (7 << 24) /* Sel7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_800MV_3_5DB_HSW (8 << 24) /* Sel8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_EMP_MASK (0xf << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_BUF_IS_IDLE (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_A_4_LANES (1 << 4)</span><br><span> #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_PORT_WIDTH_X1 (0<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_PORT_WIDTH_X2 (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_PORT_WIDTH_X4 (3<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDI_INIT_DISPLAY_DETECTED (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_PORT_WIDTH_X1 (0 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_PORT_WIDTH_X2 (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_PORT_WIDTH_X4 (3 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDI_INIT_DISPLAY_DETECTED (1 << 0)</span><br><span> </span><br><span> /* DDI Buffer Translations */</span><br><span> #define DDI_BUF_TRANS_A 0x64E00</span><br><span>@@ -4278,16 +4278,16 @@</span><br><span> #define SBI_ADDR 0xC6000</span><br><span> #define SBI_DATA 0xC6004</span><br><span> #define SBI_CTL_STAT 0xC6008</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_CTL_DEST_ICLK (0x0<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_CTL_DEST_MPHY (0x1<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_CTL_OP_IORD (0x2<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_CTL_OP_IOWR (0x3<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_CTL_OP_CRRD (0x6<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_CTL_OP_CRWR (0x7<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_RESPONSE_FAIL (0x1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_RESPONSE_SUCCESS (0x0<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_BUSY (0x1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_READY (0x0<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_CTL_DEST_ICLK (0x0 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_CTL_DEST_MPHY (0x1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_CTL_OP_IORD (0x2 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_CTL_OP_IOWR (0x3 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_CTL_OP_CRRD (0x6 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_CTL_OP_CRWR (0x7 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_RESPONSE_FAIL (0x1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_RESPONSE_SUCCESS (0x0 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_BUSY (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_READY (0x0 << 0)</span><br><span> </span><br><span> /* SBI offsets */</span><br><span> #define SBI_SSCDIVINTPHASE6 0x0600</span><br><span>@@ -4296,81 +4296,81 @@</span><br><span> #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)</span><br><span> #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)</span><br><span> #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)</span><br><span> #define SBI_SSCCTL 0x020c</span><br><span> #define SBI_SSCCTL6 0x060C</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_SSCCTL_PATHALT (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_SSCCTL_DISABLE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_SSCCTL_PATHALT (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_SSCCTL_DISABLE (1 << 0)</span><br><span> #define SBI_SSCAUXDIV6 0x0610</span><br><span> #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)</span><br><span> #define SBI_DBUFF0 0x2a00</span><br><span style="color: hsl(0, 100%, 40%);">-#define SBI_DBUFF0_ENABLE (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBI_DBUFF0_ENABLE (1 << 0)</span><br><span> </span><br><span> /* LPT PIXCLK_GATE */</span><br><span> #define PIXCLK_GATE 0xC6020</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIXCLK_GATE_UNGATE (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIXCLK_GATE_GATE (0<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIXCLK_GATE_UNGATE (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIXCLK_GATE_GATE (0 << 0)</span><br><span> </span><br><span> /* SPLL */</span><br><span> #define SPLL_CTL 0x46020</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPLL_PLL_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPLL_PLL_SSC (1<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPLL_PLL_NON_SSC (2<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPLL_PLL_FREQ_810MHz (0<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPLL_PLL_FREQ_1350MHz (1<<26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPLL_PLL_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPLL_PLL_SSC (1 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPLL_PLL_NON_SSC (2 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPLL_PLL_FREQ_810MHz (0 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPLL_PLL_FREQ_1350MHz (1 << 26)</span><br><span> </span><br><span> /* WRPLL */</span><br><span> #define WRPLL_CTL1 0x46040</span><br><span> #define WRPLL_CTL2 0x46060</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_PLL_ENABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_PLL_SELECT_SSC (0x01<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_PLL_ENABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_PLL_SELECT_SSC (0x01 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_PLL_SELECT_NON_SSC (0x02 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03 << 28)</span><br><span> /* WRPLL divider programming */</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_DIVIDER_POST(x) ((x)<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_DIVIDER_POST(x) ((x) << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)</span><br><span> </span><br><span> /* Port clock selection */</span><br><span> #define PORT_CLK_SEL_A 0x46100</span><br><span> #define PORT_CLK_SEL_B 0x46104</span><br><span> #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_LCPLL_2700 (0<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_LCPLL_1350 (1<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_LCPLL_810 (2<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_SPLL (3<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_WRPLL1 (4<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_WRPLL2 (5<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PORT_CLK_SEL_NONE (7<<29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_LCPLL_2700 (0 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_LCPLL_1350 (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_LCPLL_810 (2 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_SPLL (3 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_WRPLL1 (4 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_WRPLL2 (5 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PORT_CLK_SEL_NONE (7 << 29)</span><br><span> </span><br><span> /* Transcoder clock selection */</span><br><span> #define TRANS_CLK_SEL_A 0x46140</span><br><span> #define TRANS_CLK_SEL_B 0x46144</span><br><span> #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)</span><br><span> /* For each transcoder, we need to select the corresponding port clock */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_CLK_SEL_DISABLED (0x0<<29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_CLK_SEL_DISABLED (0x0 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_CLK_SEL_PORT(x) ((x + 1) << 29)</span><br><span> </span><br><span> #define _TRANSA_MSA_MISC 0x60410</span><br><span> #define _TRANSB_MSA_MISC 0x61410</span><br><span> #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \</span><br><span> _TRANSB_MSA_MISC)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_MSA_SYNC_CLK (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_MSA_6_BPC (0<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_MSA_8_BPC (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_MSA_10_BPC (2<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_MSA_12_BPC (3<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRANS_MSA_16_BPC (4<<5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_MSA_SYNC_CLK (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_MSA_6_BPC (0 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_MSA_8_BPC (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_MSA_10_BPC (2 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_MSA_12_BPC (3 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRANS_MSA_16_BPC (4 << 5)</span><br><span> </span><br><span> /* LCPLL Control */</span><br><span> #define LCPLL_CTL 0x130040</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_PLL_DISABLE (1UL<<31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_PLL_LOCK (1<<30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_CLK_FREQ_MASK (3<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_CLK_FREQ_450 (0<<26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_CD_CLOCK_DISABLE (1<<25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LCPLL_CD_SOURCE_FCLK (1<<21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_PLL_DISABLE (1UL << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_PLL_LOCK (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_CLK_FREQ_MASK (3 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_CLK_FREQ_450 (0 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_CD_CLOCK_DISABLE (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LCPLL_CD_SOURCE_FCLK (1 << 21)</span><br><span> </span><br><span> /* Pipe WM_LINETIME - watermark line time */</span><br><span> #define PIPE_WM_LINETIME_A 0x45270</span><br><span>@@ -4379,22 +4379,22 @@</span><br><span> PIPE_WM_LINETIME_B)</span><br><span> #define PIPE_WM_LINETIME_MASK (0x1ff)</span><br><span> #define PIPE_WM_LINETIME_TIME(x) ((x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)</span><br><span> </span><br><span> /* SFUSE_STRAP */</span><br><span> #define SFUSE_STRAP 0xc2014</span><br><span style="color: hsl(0, 100%, 40%);">-#define SFUSE_STRAP_DDIB_DETECTED (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SFUSE_STRAP_DDIC_DETECTED (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SFUSE_STRAP_DDID_DETECTED (1<<0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SFUSE_STRAP_DDID_DETECTED (1 << 0)</span><br><span> </span><br><span> #define WM_DBG 0x45280</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM_DBG_DISALLOW_MAXFIFO (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WM_DBG_DISALLOW_SPRITE (1<<2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WM_DBG_DISALLOW_SPRITE (1 << 2)</span><br><span> </span><br><span> /* North Display Engine Reset Warn Options */</span><br><span> #define NDE_RSTWRN_OPT 0x46408</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_PCH_HNDSHK_EN (1<<4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RST_PCH_HNDSHK_EN (1 << 4)</span><br><span> </span><br><span> #endif /* _I915_REG_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26366">change 26366</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icee8ea01ca846f559f3a38da48325733407c302e </div>
<div style="display:none"> Gerrit-Change-Number: 26366 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>