<p>Justin TerAvest has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26342">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Add devicetree for Bip<br><br>Bip should have different devicetree entries than Yorp; it doesn't have<br>a DA7219 audio codec (instead it uses ALC5682).<br><br>BRANCH=none<br>BUG=b:79771967<br>TEST=boot, no longer see DA7219 ACPI in console.<br><br>Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38<br>Signed-off-by: Justin TerAvest <teravest@chromium.org><br>---<br>M src/mainboard/google/octopus/Kconfig<br>A src/mainboard/google/octopus/variants/bip/devicetree.cb<br>2 files changed, 195 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/26342/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig</span><br><span>index 3254ec6..79af95c 100644</span><br><span>--- a/src/mainboard/google/octopus/Kconfig</span><br><span>+++ b/src/mainboard/google/octopus/Kconfig</span><br><span>@@ -46,6 +46,7 @@</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/bip/devicetree.cb" if BOARD_GOOGLE_BIP</span><br><span> default "variants/baseboard/devicetree.cb"</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span>diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..860ca79</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>@@ -0,0 +1,194 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt</span><br><span style="color: hsl(120, 100%, 40%);">+ # Disable unused clkreq of PCIe root ports</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak)</span><br><span style="color: hsl(120, 100%, 40%);">+ # as it is required for detection</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_deemphasis_enable[2]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set de-emphasis to default (enabled) for remaining ports</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_deemphasis_enable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_deemphasis_enable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_deemphasis_enable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_deemphasis_enable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_deemphasis_enable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO for PERST_0 (WLAN_PE_RST)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "prt0_gpio" = "GPIO_164"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route, i.e., if this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed. This sets the PMC register</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE_CFG fields.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPE_NW_63_32"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "PMC_GPE_N_95_64"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw3" = "PMC_GPE_NW_31_0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PL1 override 8000 mW: Due to error in the energy calculation for</span><br><span style="color: hsl(120, 100%, 40%);">+ # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span style="color: hsl(120, 100%, 40%);">+ # be reached when RAPL PL1 is set to 8W.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl1_override_mw" = "8000"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set RAPL PL2 to 15W.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl2_override_mw" = "15000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Minimum SLP S3 assertion width 28ms.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "slp_s3_assertion_width_usecs" = "28000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable lpss s0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "lpss_s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Audio Clock and Power gating</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hdaudio_clk_gate_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hdaudio_pwr_gate_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hdaudio_bios_config_lockdown" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # digitizer at 400kHz</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[0]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 152,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 30,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable I2C5 for audio codec at 400kHz</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[5]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 104,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 52,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # trackpad at 400kHz</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[6]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 114,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 164,</span><br><span style="color: hsl(120, 100%, 40%);">+ .data_hold_time_ns = 350,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # touchscreen at 400kHz</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[7]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 76,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 164,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ # communication before memory is up.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gspi[0]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pnp_settings" = "PNP_PERF_POWER"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # - Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.1 on end # - DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.2 off end # - NPK</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # - Gen</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 on end # - Iunit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.0 on end # - CNVi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end # - P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.1 on end # - PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.2 on end # - Fast SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.3 on end # - Shared SRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/max98357a</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_delay" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device generic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0f.0 on end # - Heci1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0f.1 on end # - Heci2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0f.2 on end # - Heci3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 off end # - ISH</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 off end # - SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - PCIe-A 0 Onboard M2 Slot(Wifi)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.1 off end # - PCIe-A 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.2 off end # - PCIe-A 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.3 off end # - PCIe-A 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 off end # - PCIe-B 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # - PCIe-B 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # - XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # - XDCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/hid</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.hid" = ""WCOM50C1""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.desc" = ""WCOM Digitizer""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.has_power_resource" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid_desc_reg_offset" = "0x1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 0x9 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 on end # - I2C 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 on end # - I2C 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on end # - I2C 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # - I2C 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.1 on end # - I2C 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0000""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchpad""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW2_02"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "probed" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 15 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0001""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchscreen""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "probed" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_delay_ms" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_delay_ms" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_resource" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 10 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # - UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 off end # - UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # - UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 off end # - UART 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - GSPI 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # - SPI 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # - SPI 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # - PWM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # - eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # - SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - ESPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # - SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26342">change 26342</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26342"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38 </div>
<div style="display:none"> Gerrit-Change-Number: 26342 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Justin TerAvest <teravest@chromium.org> </div>