<p>Srinidhi N Kaushik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26285">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3<br><br>Update FSP header files to match FSP Reference Code Release v2.0.3 for<br>Gemimilake<br><br>Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257<br>Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>3 files changed, 34 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/26285/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h</span><br><span>index 354dd8a..20bd9af 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h</span><br><span>@@ -1,6 +1,6 @@</span><br><span> /** @file</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span> </span><br><span> Redistribution and use in source and binary forms, with or without modification,</span><br><span> are permitted provided that the following conditions are met:</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>index 1898c09..2045385 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>@@ -998,9 +998,23 @@</span><br><span> **/</span><br><span> UINT32 CpuPeiApWakeupBufferAddr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0180</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0180 - SkipPciePowerSequence</span><br><span style="color: hsl(120, 100%, 40%);">+ UPD To Skip PciePowerSequence, set this UPD to 0 by default on windows.</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmUpd[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipPciePowerSequence;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0181</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevAligmentFspmUpd[7];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0188 - SkipMemoryTestUpd</span><br><span style="color: hsl(120, 100%, 40%);">+ UPD To Skip CpuMemoryTest, set this UPD to 0 by default on windows.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipMemoryTestUpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0189</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpd[7];</span><br><span> } FSP_M_CONFIG;</span><br><span> </span><br><span> /** Fsp M UPD Configuration</span><br><span>@@ -1019,9 +1033,9 @@</span><br><span> **/</span><br><span> FSP_M_CONFIG FspmConfig;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0184</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0190</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1[130];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[118];</span><br><span> </span><br><span> /** Offset 0x0206</span><br><span> **/</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>index 970f0e2..1cbcb69 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>@@ -1708,9 +1708,16 @@</span><br><span> **/</span><br><span> UINT8 UsbPdoProgramming;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03AA</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AA - Skip LPSS SPI Private Clock Parameter Programming</span><br><span style="color: hsl(120, 100%, 40%);">+ When this is skipped, boot loader must program LPSS SPI PCP. 0: Initialize(Default),</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>1: Skip</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsUpd[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipSpiPCP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsUpd[5];</span><br><span> } FSP_S_CONFIG;</span><br><span> </span><br><span> /** Fsp S SGX Configuration</span><br><span>@@ -1764,7 +1771,7 @@</span><br><span> </span><br><span> /** Offset 0x03F8</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsSgxUpd[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsSgxUpd[8];</span><br><span> } FSP_S_SGX_CONFIG;</span><br><span> </span><br><span> /** Fsp S UPD Configuration</span><br><span>@@ -1787,7 +1794,11 @@</span><br><span> **/</span><br><span> FSP_S_SGX_CONFIG FspsSgxConfig;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03FE</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0400</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace9[6];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0406</span><br><span> **/</span><br><span> UINT16 UpdTerminator;</span><br><span> } FSPS_UPD;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26285">change 26285</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257 </div>
<div style="display:none"> Gerrit-Change-Number: 26285 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> </div>