<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26289">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">util/msr: Add Pentium D support<br><br>Add CPUID: F6x to Pentium_D.<br>It will not support all MSRs on intel_pentium4_later.<br>Here is the values I got on CPU model_F65:<br>https://pastebin.com/JQf7qWYn<br><br>Change-Id: Ic6ac0593607b6f87fe921ac52738dad5ee3457dc<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/Kconfig<br>M src/arch/x86/c_start.S<br>M src/arch/x86/include/arch/cpu.h<br>M util/msrtool/Makefile.in<br>A util/msrtool/intel_pentium_D.c<br>M util/msrtool/msrtool.c<br>M util/msrtool/msrtool.h<br>7 files changed, 568 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26289/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/Kconfig b/src/Kconfig</span><br><span>index 99a704d..73e6fcd 100644</span><br><span>--- a/src/Kconfig</span><br><span>+++ b/src/Kconfig</span><br><span>@@ -395,6 +395,11 @@</span><br><span> default 0x1000 if ARCH_X86</span><br><span> default 0x0</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config STACK_ALIGNMENT_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1000 if ARCH_X86</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAX_CPUS</span><br><span> int</span><br><span> default 1</span><br><span>diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S</span><br><span>index 6426ef3..b9573ba 100644</span><br><span>--- a/src/arch/x86/c_start.S</span><br><span>+++ b/src/arch/x86/c_start.S</span><br><span>@@ -19,7 +19,7 @@</span><br><span> .global _stack</span><br><span> .global _estack</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-.align CONFIG_STACK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+.align CONFIG_STACK_ALIGNMENT_SIZE</span><br><span> _stack:</span><br><span> .space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE</span><br><span> _estack:</span><br><span>diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h</span><br><span>index 5d44aae..7d0f182 100644</span><br><span>--- a/src/arch/x86/include/arch/cpu.h</span><br><span>+++ b/src/arch/x86/include/arch/cpu.h</span><br><span>@@ -206,8 +206,8 @@</span><br><span> "orl %2, %0 "</span><br><span> #endif</span><br><span> : "=r" (ci)</span><br><span style="color: hsl(0, 100%, 40%);">- : "0" (~(CONFIG_STACK_SIZE - 1)),</span><br><span style="color: hsl(0, 100%, 40%);">- "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info))</span><br><span style="color: hsl(120, 100%, 40%);">+ : "0" (~(CONFIG_STACK_ALIGNMENT_SIZE - 1)),</span><br><span style="color: hsl(120, 100%, 40%);">+ "r" (CONFIG_STACK_ALIGNMENT_SIZE - sizeof(struct cpu_info))</span><br><span> );</span><br><span> return ci;</span><br><span> }</span><br><span>diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in</span><br><span>index 3d50f4c..9b3e9d3 100644</span><br><span>--- a/util/msrtool/Makefile.in</span><br><span>+++ b/util/msrtool/Makefile.in</span><br><span>@@ -22,7 +22,7 @@</span><br><span> CFLAGS = @CFLAGS@</span><br><span> LDFLAGS = @LDFLAGS@</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o</span><br><span style="color: hsl(120, 100%, 40%);">+TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_pentium_D.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o</span><br><span> SYSTEMS = linux.o darwin.o freebsd.o</span><br><span> OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS)</span><br><span> </span><br><span>diff --git a/util/msrtool/intel_pentium_D.c b/util/msrtool/intel_pentium_D.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d4a940a</span><br><span>--- /dev/null</span><br><span>+++ b/util/msrtool/intel_pentium_D.c</span><br><span>@@ -0,0 +1,554 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of msrtool.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "msrtool.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int intel_pentium_D_probe(const struct targetdef *target, const struct cpuid_t *id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((VENDOR_INTEL == id->vendor) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf == id->family) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x6 == id->model));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct msrdef intel_pentium_D_msrs[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0000, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0001, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0006, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0010, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0017, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x001B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x002A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x002B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWERON", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x002C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_FREQUENCY_ID", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x008B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00FE, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x017A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x018A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x019A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x019B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x019C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x019D, MSRTYPE_RDWR, MSR2(0, 0), "GV_THERM", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01A0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01A1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PLATFORM_BRV", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01A2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TEMPERATURE_TARGET", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01D7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01D8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01D9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01DA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x020A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x020B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x020C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x020D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x020E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x020F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x026A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x026B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x026C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x026D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x026E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x026F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x02FF, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x030A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x030B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x030C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x030D, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x030E, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x030F, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0345, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x036A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x036B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x036C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x036D, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x036E, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x036F, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03A9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03AA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03AB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03AC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03AD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03AE, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03AF, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03B9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03BA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03BB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03BC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03BD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03BE, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03C9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03CA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03CB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03CC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03CD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03E0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03E1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03F0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03F1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x03F2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x040C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x040D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x040E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x040F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", {</span><br><span style="color: hsl(120, 100%, 40%);">+ { BITS_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+ }},</span><br><span style="color: hsl(120, 100%, 40%);">+ { MSR_EOT }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c</span><br><span>index 9be83f4..0cf96e6 100644</span><br><span>--- a/util/msrtool/msrtool.c</span><br><span>+++ b/util/msrtool/msrtool.c</span><br><span>@@ -47,6 +47,7 @@</span><br><span> { "intel_core2_later", "Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000 series", intel_core2_later_probe, intel_core2_later_msrs },</span><br><span> { "intel_pentium4_early", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4 processors", intel_pentium4_early_probe, intel_pentium4_early_msrs },</span><br><span> { "intel_pentium4_later", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4, Pentium D processors", intel_pentium4_later_probe, intel_pentium4_later_msrs },</span><br><span style="color: hsl(120, 100%, 40%);">+ { "intel_pentium_D", "Intel Pentium D processors", intel_pentium_D_probe, intel_pentium_D_msrs },</span><br><span> { "intel_nehalem", "Intel Core i5, i7 Processors, Intel Xeon Processor 3400, 3500, 5500, based on Nehalem architecture", intel_nehalem_probe, intel_nehalem_msrs },</span><br><span> { "intel_atom", "Intel Atom Processors, N450", intel_atom_probe, intel_atom_msrs },</span><br><span> { TARGET_EOT }</span><br><span>diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h</span><br><span>index 35559c2..dc7f1f0 100644</span><br><span>--- a/util/msrtool/msrtool.h</span><br><span>+++ b/util/msrtool/msrtool.h</span><br><span>@@ -244,6 +244,10 @@</span><br><span> extern int intel_pentium4_later_probe(const struct targetdef *t, const struct cpuid_t *id);</span><br><span> extern const struct msrdef intel_pentium4_later_msrs[];</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* intel_pentium_D.c */</span><br><span style="color: hsl(120, 100%, 40%);">+extern int intel_pentium_D_probe(const struct targetdef *t, const struct cpuid_t *id);</span><br><span style="color: hsl(120, 100%, 40%);">+extern const struct msrdef intel_pentium_D_msrs[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* intel_nehalem.c */</span><br><span> extern int intel_nehalem_probe(const struct targetdef *t, const struct cpuid_t *id);</span><br><span> extern const struct msrdef intel_nehalem_msrs[];</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26289">change 26289</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26289"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic6ac0593607b6f87fe921ac52738dad5ee3457dc </div>
<div style="display:none"> Gerrit-Change-Number: 26289 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>