<p>Evgeny Zinoviev has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26299">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/lenovo: Add ThinkPad W530 support<br><br>Tested and working:<br> - Wi-Fi<br> - Ethernet<br> - Bluetooth<br> - Speakers<br> - Internal mic<br> - SD card reader<br> - Suspend and resume<br> - Keyboard, touchpad, trackpoint<br> - Fan<br> - Webcam<br> - 4 RAM slots<br> - All USB ports<br> - VGA ROM (FIXME: black screen after resume from s3)<br> - Native graphics initialization (FIXME: probably incorrect panel frequency, etc. in GRUB; in linux everything's fine incl. resume from s3)<br> - GRUB payload<br> - Internal flashing using flashrom<br><br>Not tested yet:<br> - WWAN<br> - Fingerprint reader<br> - Colorimeter<br> - Smart card reader<br> - Docking station<br> - VGA output<br> - Optical disc drive<br> - Discrete graphics<br><br>TODO:<br> - Test BDC detection<br><br>Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400<br>Signed-off-by: Evgeny Zinoviev <me@ch1p.com><br><br>add vbt<br><br>Change-Id: I3e6ce7dc6e5cb68d7b4b5249fcfc297940866297<br>---<br>M src/mainboard/lenovo/t530/Kconfig<br>M src/mainboard/lenovo/t530/Kconfig.name<br>M src/mainboard/lenovo/t530/Makefile.inc<br>M src/mainboard/lenovo/t530/board_info.txt<br>M src/mainboard/lenovo/t530/romstage.c<br>A src/mainboard/lenovo/t530/variants/t530/board_info.txt<br>R src/mainboard/lenovo/t530/variants/t530/data.vbt<br>R src/mainboard/lenovo/t530/variants/t530/devicetree.cb<br>R src/mainboard/lenovo/t530/variants/t530/gpio.c<br>A src/mainboard/lenovo/t530/variants/t530/romstage.c<br>A src/mainboard/lenovo/t530/variants/w530/board_info.txt<br>A src/mainboard/lenovo/t530/variants/w530/data.vbt<br>A src/mainboard/lenovo/t530/variants/w530/devicetree.cb<br>A src/mainboard/lenovo/t530/variants/w530/gpio.c<br>A src/mainboard/lenovo/t530/variants/w530/romstage.c<br>15 files changed, 590 insertions(+), 32 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/26299/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig</span><br><span>index 065fd3c..36659d8 100644</span><br><span>--- a/src/mainboard/lenovo/t530/Kconfig</span><br><span>+++ b/src/mainboard/lenovo/t530/Kconfig</span><br><span>@@ -1,7 +1,5 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_LENOVO_T530</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LENOVO_BASEBOARD_T530</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span> select CPU_INTEL_SOCKET_RPGA989</span><br><span> select NORTHBRIDGE_INTEL_IVYBRIDGE</span><br><span>@@ -24,6 +22,8 @@</span><br><span> # Workaround for EC/KBC IRQ1.</span><br><span> select SERIRQ_CONTINUOUS_MODE</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_LENOVO_BASEBOARD_T530</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config HAVE_IFD_BIN</span><br><span> bool</span><br><span> default n</span><br><span>@@ -32,13 +32,24 @@</span><br><span> bool</span><br><span> default n</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "t530" if BOARD_LENOVO_T530</span><br><span style="color: hsl(120, 100%, 40%);">+ default "w530" if BOARD_LENOVO_W530</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAINBOARD_DIR</span><br><span> string</span><br><span> default lenovo/t530</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/t530/devicetree.cb" if BOARD_LENOVO_T530</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/w530/devicetree.cb" if BOARD_LENOVO_W530</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "ThinkPad T530"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad T530" if BOARD_LENOVO_T530</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad W530" if BOARD_LENOVO_W530</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>@@ -54,7 +65,8 @@</span><br><span> </span><br><span> config VGA_BIOS_FILE</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "pci8086,0106.rom"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "pci8086,0106.rom" if BOARD_LENOVO_T530</span><br><span style="color: hsl(120, 100%, 40%);">+ default "pci8086,0166.rom" if BOARD_LENOVO_W530</span><br><span> </span><br><span> config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span> hex</span><br><span>@@ -68,4 +80,4 @@</span><br><span> bool</span><br><span> default y</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-endif # BOARD_LENOVO_T530</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/lenovo/t530/Kconfig.name b/src/mainboard/lenovo/t530/Kconfig.name</span><br><span>index b5dee66..9bcd2c5 100644</span><br><span>--- a/src/mainboard/lenovo/t530/Kconfig.name</span><br><span>+++ b/src/mainboard/lenovo/t530/Kconfig.name</span><br><span>@@ -1,2 +1,7 @@</span><br><span> config BOARD_LENOVO_T530</span><br><span style="color: hsl(0, 100%, 40%);">- bool "ThinkPad T530"</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "ThinkPad T530"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_LENOVO_BASEBOARD_T530</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LENOVO_W530</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "ThinkPad W530"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_LENOVO_BASEBOARD_T530</span><br><span>diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc</span><br><span>index 9eb141a..5c450eb 100644</span><br><span>--- a/src/mainboard/lenovo/t530/Makefile.inc</span><br><span>+++ b/src/mainboard/lenovo/t530/Makefile.inc</span><br><span>@@ -14,4 +14,5 @@</span><br><span> ##</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += variants/$(VARIANT_DIR)/gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += variants/$(VARIANT_DIR)/romstage.c</span><br><span>diff --git a/src/mainboard/lenovo/t530/board_info.txt b/src/mainboard/lenovo/t530/board_info.txt</span><br><span>index 09ddde1..a659fe0 100644</span><br><span>--- a/src/mainboard/lenovo/t530/board_info.txt</span><br><span>+++ b/src/mainboard/lenovo/t530/board_info.txt</span><br><span>@@ -1,3 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Lenovo</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: ThinkPad T530 baseboard</span><br><span> Category: laptop</span><br><span> ROM package: SOIC-8</span><br><span> ROM protocol: SPI</span><br><span>diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c</span><br><span>index d2f7390..7470acc 100644</span><br><span>--- a/src/mainboard/lenovo/t530/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t530/romstage.c</span><br><span>@@ -22,7 +22,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span> #include <southbridge/intel/common/rcba.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h></span><br><span> #include <device/device.h></span><br><span>@@ -70,28 +69,6 @@</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 1, -1 }, /* P3: WWAN slot, no OC */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 1, 2 }, /* P4: yellow USB, OC 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0, 0, -1 }, /* P6: color sensor(w530), no OC */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 2, -1 }, /* P7: docking, no OC */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 0, -1 }, /* P8: smart card reader, no OC */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 0, -1 }, /* P10: fingerprint reader, no OC */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 0, -1 }, /* P11: bluetooth, no OC. */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 1, -1 }, /* P13: camera, no OC */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_get_spd(spd_raw_data *spd, bool id_only) {</span><br><span style="color: hsl(0, 100%, 40%);">- read_spd (&spd[0], 0x50, id_only);</span><br><span style="color: hsl(0, 100%, 40%);">- read_spd (&spd[2], 0x51, id_only);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void mainboard_early_init(int s3resume)</span><br><span> {</span><br><span> hybrid_graphics_init();</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/t530/board_info.txt b/src/mainboard/lenovo/t530/variants/t530/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..49f09e5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/t530/board_info.txt</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Lenovo</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: ThinkPad T530</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: n</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2012</span><br><span>diff --git a/src/mainboard/lenovo/t530/data.vbt b/src/mainboard/lenovo/t530/variants/t530/data.vbt</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/lenovo/t530/data.vbt</span><br><span>rename to src/mainboard/lenovo/t530/variants/t530/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/lenovo/t530/devicetree.cb</span><br><span>rename to src/mainboard/lenovo/t530/variants/t530/devicetree.cb</span><br><span>diff --git a/src/mainboard/lenovo/t530/gpio.c b/src/mainboard/lenovo/t530/variants/t530/gpio.c</span><br><span>similarity index 93%</span><br><span>rename from src/mainboard/lenovo/t530/gpio.c</span><br><span>rename to src/mainboard/lenovo/t530/variants/t530/gpio.c</span><br><span>index daadc3e..84f2ca1 100644</span><br><span>--- a/src/mainboard/lenovo/t530/gpio.c</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/t530/gpio.c</span><br><span>@@ -1,3 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span> .gpio0 = GPIO_MODE_GPIO,</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6d15788</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[0], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x51, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* P3: WWAN slot, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 2 }, /* P4: yellow USB, OC 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, 0 }, /* P6: empty */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, -1 }, /* P7: docking, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P8: smart card reader, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P10: fingerprint reader, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P11: bluetooth, no OC. */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* P13: camera, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/w530/board_info.txt b/src/mainboard/lenovo/t530/variants/w530/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..d7d3679</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/w530/board_info.txt</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Lenovo</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: ThinkPad W530</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: n</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2012</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/w530/data.vbt b/src/mainboard/lenovo/t530/variants/w530/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..4db2694</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/w530/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..f79ab9b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb</span><br><span>@@ -0,0 +1,223 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did</span><br><span style="color: hsl(120, 100%, 40%);">+ # IGD Displays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DisplayPort Hotplug with 6ms pulse</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_d_hotplug" = "0x06"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_b_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_c_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Panel as LVDS and configure power delays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "0" # LVDS</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.link_frequency_270_mhz" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x1155"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x11551155"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_rPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax # FIXME: check all registers</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pci_mmio_size" = "2048"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPI routing</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0 No effect (default)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 2 SCI (if corresponding GPIO_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "alt_gp_smi_en" = "0x0000"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi1_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi13_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "0x0065"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "docking_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x007c1601"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c15e1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen4_dec" = "0x000c06a1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "superspeed_capable_ports" = "0x0000000f"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_overcurrent_mapping" = "0x04000201"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_switchable_ports" = "0x0000000f"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # USB 3.0 Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on # USB2 EHCI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # High Definition Audio Audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/ricoh/rce822 # Ricoh cardreader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "disable_mask" = "0x83"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdwppol" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Ricoh SD card reader</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off # PCIe Port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off # PCIe Port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # USB2 EHCI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge PCI-LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/pmh7</span><br><span style="color: hsl(120, 100%, 40%);">+ register "backlight_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dock_event_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.1 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/h8 # FIXME: has_uwb</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask0" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask1" = "0x86"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config0" = "0xa6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config1" = "0x09"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config2" = "0xa0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config3" = "0x02"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event2_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event3_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event4_enable" = "0xd0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event5_enable" = "0xfc"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event6_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event7_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event8_enable" = "0x7b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event9_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventa_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventb_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventc_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventd_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "evente_enable" = "0x0d"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_keyboard_backlight" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_management_beeps" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_bdc_detection" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bdc_gpio_num" = "54"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bdc_gpio_lvl" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.2 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x1600</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x66 = 0x1604</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/lenovo/hybrid_graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.f on end # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "detect_gpio" = "21"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_panel_hybrid_gpio" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "panel_hybrid_gpio" = "52"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "panel_integrated_lvl" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_backlight_gpio" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_dgpu_power_gpio" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_thinker1" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 54 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 55 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 56 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 57 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5c on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5d on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5e on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5f on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off # SATA Controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Host bridge Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on # Internal graphics VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f5</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/w530/gpio.c b/src/mainboard/lenovo/t530/variants/w530/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8eb776b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/w530/gpio.c</span><br><span>@@ -0,0 +1,219 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c2d5bd7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[0], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[1], 0x52, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x51, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[3], 0x53, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* P3: WWAN slot, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 2 }, /* P4: yellow USB, OC 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, -1 }, /* P6: color sensor, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, -1 }, /* P7: docking, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P8: smart card reader, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P10: fingerprint reader, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P11: bluetooth, no OC. */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* P13: camera, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26299">change 26299</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26299"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3e6ce7dc6e5cb68d7b4b5249fcfc297940866297 </div>
<div style="display:none"> Gerrit-Change-Number: 26299 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Evgeny Zinoviev <me@ch1p.com> </div>