<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26296">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/ibexpeak: Use common Intel SMM code<br><br>TODO in followup patch: Some not mainboard specific things should be<br>moved out of mainboard_smi_apmc.<br><br>Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/x201/smihandler.c<br>M src/mainboard/packardbell/ms2290/smihandler.c<br>M src/southbridge/intel/ibexpeak/Kconfig<br>M src/southbridge/intel/ibexpeak/Makefile.inc<br>M src/southbridge/intel/ibexpeak/pch.h<br>D src/southbridge/intel/ibexpeak/smi.c<br>M src/southbridge/intel/ibexpeak/smihandler.c<br>7 files changed, 17 insertions(+), 1,038 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/26296/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c</span><br><span>index f00ae0d..3c5b3de 100644</span><br><span>--- a/src/mainboard/lenovo/x201/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/x201/smihandler.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/smm.h></span><br><span> #include "southbridge/intel/ibexpeak/nvs.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/intel/ibexpeak/pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span> #include "southbridge/intel/ibexpeak/me.h"</span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span> #include <cpu/intel/model_2065x/model_2065x.h></span><br><span>diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>index eeb55df..c097dfd 100644</span><br><span>--- a/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>+++ b/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/smm.h></span><br><span> #include "southbridge/intel/ibexpeak/nvs.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/intel/ibexpeak/pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span> #include "southbridge/intel/ibexpeak/me.h"</span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span> #include <cpu/intel/model_2065x/model_2065x.h></span><br><span>diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig</span><br><span>index 5cf402c..004cdd8 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/Kconfig</span><br><span>+++ b/src/southbridge/intel/ibexpeak/Kconfig</span><br><span>@@ -32,6 +32,7 @@</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_SMM</span><br><span> select HAVE_USBDEBUG_OPTIONS</span><br><span> select COMMON_FADT</span><br><span> select ACPI_SATA_GENERATOR</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc</span><br><span>index 7714f95..45fe48d 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/ibexpeak/Makefile.inc</span><br><span>@@ -37,7 +37,6 @@</span><br><span> ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c</span><br><span> ramstage-y += madt.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += smi.c</span><br><span> smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c</span><br><span> </span><br><span> romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index d3c5a66..844c688 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -63,7 +63,6 @@</span><br><span> int pch_silicon_type(void);</span><br><span> int pch_silicon_supported(int type, int rev);</span><br><span> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);</span><br><span style="color: hsl(0, 100%, 40%);">-void gpi_route_interrupt(u8 gpi, u8 mode);</span><br><span> #if IS_ENABLED(CONFIG_ELOG)</span><br><span> void pch_log_state(void);</span><br><span> #endif</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c</span><br><span>deleted file mode 100644</span><br><span>index 9f6badb..0000000</span><br><span>--- a/src/southbridge/intel/ibexpeak/smi.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,348 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/smm/gen1/smi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* While we read PMBASE dynamically in case it changed, let's</span><br><span style="color: hsl(0, 100%, 40%);">- * initialize it with a sane value</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 pmbase = DEFAULT_PMBASE;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return PM1_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_pm1_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_pm1_status(u16 pm1_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PM1_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_smi_status(u32 smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return GPE0_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_gpe0_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_gpe0_status(u32 gpe0_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i=31; i>= 16; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear ALT_GP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return ALT_GP_SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_alt_gp_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inl(pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i=15; i>= 0; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear TCOx_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return TCOx_STS registers</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tcobase = pmbase + 0x60;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(tcobase + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_tco_status(u32 tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Set the EOS bit</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void smi_set_eos(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= EOS;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smm_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smi_en;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pm1_en;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpe0_en;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ELOG)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Log events from chipset before clearing */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_log_state();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Initializing southbridge SMI...");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- PMBASE) & 0xff80;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_en & APMC_EN) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SMI# handler already enabled?\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smi_status(reset_smi_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_pm1_status(reset_pm1_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_gpe0_status(reset_gpe0_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_alt_gp_smi_status(reset_alt_gp_smi_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_tco_status(reset_tco_status());</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable GPE0 PME_B0 */</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_en = inl(pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_en &= ~PME_B0_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0_en, pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en |= PWRBTN_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en |= GBL_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(pm1_en, pmbase + PM1_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable SMI generation:</span><br><span style="color: hsl(0, 100%, 40%);">- * - on TCO events</span><br><span style="color: hsl(0, 100%, 40%);">- * - on APMC writes (io 0xb2)</span><br><span style="color: hsl(0, 100%, 40%);">- * - on writes to SLP_EN (sleep states)</span><br><span style="color: hsl(0, 100%, 40%);">- * - on writes to GBL_RLS (bios commands)</span><br><span style="color: hsl(0, 100%, 40%);">- * No SMIs:</span><br><span style="color: hsl(0, 100%, 40%);">- * - on microcontroller writes (io 0x62/0x66)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = 0; /* reset SMI enables */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= TCO_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= APMC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#if DEBUG_PERIODIC_SMIS</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using</span><br><span style="color: hsl(0, 100%, 40%);">- * periodic SMIs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= PERIODIC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= SLP_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= BIOS_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The following need to be on for SMIs to happen */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= EOS | GBL_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outl(smi_en, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_trigger_smi(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /**</span><br><span style="color: hsl(0, 100%, 40%);">- * There are several methods of raising a controlled SMI# via</span><br><span style="color: hsl(0, 100%, 40%);">- * software, among them:</span><br><span style="color: hsl(0, 100%, 40%);">- * - Writes to io 0xb2 (APMC)</span><br><span style="color: hsl(0, 100%, 40%);">- * - Writes to the Local Apic ICR with Delivery mode SMI.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Using the local apic is a bit more tricky. According to</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD Family 11 Processor BKDG no destination shorthand must be</span><br><span style="color: hsl(0, 100%, 40%);">- * used.</span><br><span style="color: hsl(0, 100%, 40%);">- * The whole SMM initialization is quite a bit hardware specific, so</span><br><span style="color: hsl(0, 100%, 40%);">- * I'm not too worried about the better of the methods at the moment</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* raise an SMI interrupt */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... raise SMI#\n");</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x00, 0xb2);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_clear_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear SMI status */</span><br><span style="color: hsl(0, 100%, 40%);">- reset_smi_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear PM1 status */</span><br><span style="color: hsl(0, 100%, 40%);">- reset_pm1_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set EOS bit so other SMIs can occur. */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_set_eos();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Issue SMI to set the gnvs pointer in SMM.</span><br><span style="color: hsl(0, 100%, 40%);">- * tcg and smi1 are unused.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * EAX = APM_CNT_GNVS_UPDATE</span><br><span style="color: hsl(0, 100%, 40%);">- * EBX = gnvs pointer</span><br><span style="color: hsl(0, 100%, 40%);">- * EDX = APM_CNT</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile (</span><br><span style="color: hsl(0, 100%, 40%);">- "outb %%al, %%dx\n\t"</span><br><span style="color: hsl(0, 100%, 40%);">- : /* ignore result */</span><br><span style="color: hsl(0, 100%, 40%);">- : "a" (APM_CNT_GNVS_UPDATE),</span><br><span style="color: hsl(0, 100%, 40%);">- "b" ((u32)gnvs),</span><br><span style="color: hsl(0, 100%, 40%);">- "d" (APM_CNT)</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>index 12a7ac0..f4b5327 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>@@ -35,17 +35,7 @@</span><br><span> #include "northbridge/intel/nehalem/nehalem.h"</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* While we read PMBASE dynamically in case it changed, let's</span><br><span style="color: hsl(0, 100%, 40%);">- * initialize it with a sane value</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 pmbase = DEFAULT_PMBASE;</span><br><span style="color: hsl(0, 100%, 40%);">-u16 smm_get_pmbase(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static u8 smm_initialized = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span> </span><br><span> /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located</span><br><span> * by coreboot.</span><br><span>@@ -56,193 +46,6 @@</span><br><span> return gnvs;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void alt_gpi_mask(u16 clr, u16 set)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gp &= ~clr;</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gp |= set;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(alt_gp, pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void gpe0_mask(u32 clr, u32 set)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpe0 = inl(pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0 &= ~clr;</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0 |= set;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0, pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void gpi_route_interrupt(u8 gpi, u8 mode)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpi_rout;</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpi >= 16)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gpi_mask(1 << gpi, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_mask(1 << (gpi+16), 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);</span><br><span style="color: hsl(0, 100%, 40%);">- gpi_rout &= ~(3 << (2 * gpi));</span><br><span style="color: hsl(0, 100%, 40%);">- gpi_rout |= ((mode & 3) << (2 * gpi));</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (mode == GPI_IS_SCI)</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_mask(0, 1 << (gpi+16));</span><br><span style="color: hsl(0, 100%, 40%);">- else if (mode == GPI_IS_SMI)</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gpi_mask(0, 1 << gpi);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return PM1_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_pm1_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_pm1_status(u16 pm1_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PM1_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">- int reg16 = inw(pmbase + PM1_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_smi_status(u32 smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return GPE0_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_gpe0_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_gpe0_status(u32 gpe0_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i=31; i>= 16; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear TCOx_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return TCOx_STS registers</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tcobase = pmbase + 0x60;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(tcobase + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_tco_status(u32 tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> int southbridge_io_trap_handler(int smif)</span><br><span> {</span><br><span> switch (smif) {</span><br><span>@@ -260,53 +63,6 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Set the EOS bit</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smi_set_eos(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= EOS;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void busmaster_disable_on_bus(int bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int slot, func;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int val;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char hdr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (slot = 0; slot < 0x20; slot++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (func = 0; func < 8; func++) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (val == 0xffffffff || val == 0x00000000 ||</span><br><span style="color: hsl(0, 100%, 40%);">- val == 0x0000ffff || val == 0xffff0000)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable Bus Mastering for this one device */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~PCI_COMMAND_MASTER;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* If this is a bridge, then follow it. */</span><br><span style="color: hsl(0, 100%, 40%);">- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);</span><br><span style="color: hsl(0, 100%, 40%);">- hdr &= 0x7f;</span><br><span style="color: hsl(0, 100%, 40%);">- if (hdr == PCI_HEADER_TYPE_BRIDGE ||</span><br><span style="color: hsl(0, 100%, 40%);">- hdr == PCI_HEADER_TYPE_CARDBUS) {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int buses;</span><br><span style="color: hsl(0, 100%, 40%);">- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);</span><br><span style="color: hsl(0, 100%, 40%);">- busmaster_disable_on_bus((buses >> 8) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void southbridge_gate_memory_reset_real(int offset,</span><br><span> u16 use, u16 io, u16 lvl)</span><br><span> {</span><br><span>@@ -338,7 +94,7 @@</span><br><span> * Intel reference designs all use GPIO 60 but it is</span><br><span> * not a requirement and boards could use a different pin.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_gate_memory_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_gate_memory_reset(void)</span><br><span> {</span><br><span> u16 gpiobase;</span><br><span> </span><br><span>@@ -358,377 +114,7 @@</span><br><span> gpiobase + GP_LVL);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void xhci_sleep(u8 slp_typ)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32, xhci_bar;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- switch (slp_typ) {</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S3:</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S4:</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 &= ~0x03UL;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- xhci_bar = pci_read_config32(PCH_XHCI_DEV,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_BASE_ADDRESS_0) & ~0xFUL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((xhci_bar + 0x4C0) & 1)</span><br><span style="color: hsl(0, 100%, 40%);">- pch_iobp_update(0xEC000082, ~0UL, (3 << 2));</span><br><span style="color: hsl(0, 100%, 40%);">- if ((xhci_bar + 0x4D0) & 1)</span><br><span style="color: hsl(0, 100%, 40%);">- pch_iobp_update(0xEC000182, ~0UL, (3 << 2));</span><br><span style="color: hsl(0, 100%, 40%);">- if ((xhci_bar + 0x4E0) & 1)</span><br><span style="color: hsl(0, 100%, 40%);">- pch_iobp_update(0xEC000282, ~0UL, (3 << 2));</span><br><span style="color: hsl(0, 100%, 40%);">- if ((xhci_bar + 0x4F0) & 1)</span><br><span style="color: hsl(0, 100%, 40%);">- pch_iobp_update(0xEC000382, ~0UL, (3 << 2));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 |= 0x03;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S5:</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 |= ((1 << 8) | 0x03);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_sleep(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 slp_typ;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // save and recover RTC port values</span><br><span style="color: hsl(0, 100%, 40%);">- u8 tmp70, tmp72;</span><br><span style="color: hsl(0, 100%, 40%);">- tmp70 = inb(0x70);</span><br><span style="color: hsl(0, 100%, 40%);">- tmp72 = inb(0x72);</span><br><span style="color: hsl(0, 100%, 40%);">- get_option(&s5pwr, "power_on_after_fail");</span><br><span style="color: hsl(0, 100%, 40%);">- outb(tmp70, 0x70);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(tmp72, 0x72);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* First, disable further SMIs */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= ~SLP_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Figure out SLP_TYP */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);</span><br><span style="color: hsl(0, 100%, 40%);">- slp_typ = acpi_sleep_from_pm1(reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (smm_get_gnvs()->xhci)</span><br><span style="color: hsl(0, 100%, 40%);">- xhci_sleep(slp_typ);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Do any mainboard sleep handling */</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_smi_sleep(slp_typ);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ELOG_GSMI)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Log S3, S4, and S5 entry */</span><br><span style="color: hsl(0, 100%, 40%);">- if (slp_typ >= ACPI_S3)</span><br><span style="color: hsl(0, 100%, 40%);">- elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Next, do the deed.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- switch (slp_typ) {</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S3:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Gate memory reset */</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_gate_memory_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache before going to S3 */</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S5:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0, pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Always set the flag in case CMOS was changed on runtime. For</span><br><span style="color: hsl(0, 100%, 40%);">- * "KEEP", switch to "OFF" - KEEP is software emulated</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);</span><br><span style="color: hsl(0, 100%, 40%);">- if (s5pwr == MAINBOARD_POWER_ON) {</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= ~1;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* also iterates over all bridges on bus 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- busmaster_disable_on_bus(0);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write back to the SLP register to cause the originally intended</span><br><span style="color: hsl(0, 100%, 40%);">- * event again. We need to set BIT13 (SLP_EN) though to make the</span><br><span style="color: hsl(0, 100%, 40%);">- * sleep happen.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 | SLP_EN, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make sure to stop executing code here for S3/S4/S5 */</span><br><span style="color: hsl(0, 100%, 40%);">- if (slp_typ >= ACPI_S3)</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* In most sleep states, the code flow of this function ends at</span><br><span style="color: hsl(0, 100%, 40%);">- * the line above. However, if we entered sleep state S1 and wake</span><br><span style="color: hsl(0, 100%, 40%);">- * up again, we will continue to execute code in this function.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & SCI_EN) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* The OS is not an ACPI OS, so we set the state to S0 */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~(SLP_EN | SLP_TYP);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Look for Synchronous IO SMI and use save state from that</span><br><span style="color: hsl(0, 100%, 40%);">- * core in case we are not running on the same core that</span><br><span style="color: hsl(0, 100%, 40%);">- * initiated the IO transaction.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- em64t101_smm_state_save_area_t *state;</span><br><span style="color: hsl(0, 100%, 40%);">- int node;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check all nodes looking for the one that issued the IO */</span><br><span style="color: hsl(0, 100%, 40%);">- for (node = 0; node < CONFIG_MAX_CPUS; node++) {</span><br><span style="color: hsl(0, 100%, 40%);">- state = smm_get_save_state(node);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check for Synchronous IO (bit0 == 1) */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!(state->io_misc_info & (1 << 0)))</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make sure it was a write (bit4 == 0) */</span><br><span style="color: hsl(0, 100%, 40%);">- if (state->io_misc_info & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check for APMC IO port */</span><br><span style="color: hsl(0, 100%, 40%);">- if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check AX against the requested command */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((state->rax & 0xff) != cmd)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return state;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ELOG_GSMI)</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gsmi(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *ret, *param;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 sub_command;</span><br><span style="color: hsl(0, 100%, 40%);">- em64t101_smm_state_save_area_t *io_smi =</span><br><span style="color: hsl(0, 100%, 40%);">- smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!io_smi)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Command and return value in EAX */</span><br><span style="color: hsl(0, 100%, 40%);">- ret = (u32*)&io_smi->rax;</span><br><span style="color: hsl(0, 100%, 40%);">- sub_command = (u8)(*ret >> 8);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Parameter buffer in EBX */</span><br><span style="color: hsl(0, 100%, 40%);">- param = (u32*)&io_smi->rbx;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* drivers/elog/gsmi.c */</span><br><span style="color: hsl(0, 100%, 40%);">- *ret = gsmi_exec(sub_command, param);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_apmc(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pmctrl;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- em64t101_smm_state_save_area_t *state;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Emulate B2 register as the FADT / Linux expects it */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(APM_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- switch (reg8) {</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_CST_CONTROL:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Calling this function seems to cause</span><br><span style="color: hsl(0, 100%, 40%);">- * some kind of race condition in Linux</span><br><span style="color: hsl(0, 100%, 40%);">- * and causes a kernel oops</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "C-state control\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_PST_CONTROL:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Calling this function seems to cause</span><br><span style="color: hsl(0, 100%, 40%);">- * some kind of race condition in Linux</span><br><span style="color: hsl(0, 100%, 40%);">- * and causes a kernel oops</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "P-state control\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl &= ~SCI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(pmctrl, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl |= SCI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(pmctrl, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_GNVS_UPDATE:</span><br><span style="color: hsl(0, 100%, 40%);">- if (smm_initialized) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- state = smi_apmc_find_state_save(reg8);</span><br><span style="color: hsl(0, 100%, 40%);">- if (state) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* EBX in the state save contains the GNVS pointer */</span><br><span style="color: hsl(0, 100%, 40%);">- gnvs = (global_nvs_t *)((u32)state->rbx);</span><br><span style="color: hsl(0, 100%, 40%);">- smm_initialized = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ELOG_GSMI)</span><br><span style="color: hsl(0, 100%, 40%);">- case ELOG_GSMI_APM_CNT:</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_gsmi();</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_smi_apmc(reg8);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_pm1(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pm1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_sts = reset_pm1_status();</span><br><span style="color: hsl(0, 100%, 40%);">- dump_pm1_status(pm1_sts);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* While OSPM is not active, poweroff immediately</span><br><span style="color: hsl(0, 100%, 40%);">- * on a power button event.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & PWRBTN_STS) {</span><br><span style="color: hsl(0, 100%, 40%);">- // power button pressed</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = (7 << 10) | (1 << 13);</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ELOG_GSMI)</span><br><span style="color: hsl(0, 100%, 40%);">- elog_add_event(ELOG_TYPE_POWER_BUTTON);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gpe0(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpe0_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_sts = reset_gpe0_status();</span><br><span style="color: hsl(0, 100%, 40%);">- dump_gpe0_status(gpe0_sts);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gpi(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 &= inw(pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_smi_gpi(reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg16)</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_mc(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Are periodic SMIs enabled? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((reg32 & MCSMI_EN) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Microcontroller SMI.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_tco(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tco_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- tco_sts = reset_tco_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Any TCO event? */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8)) { // BIOSWR</span><br><span style="color: hsl(0, 100%, 40%);">- u8 bios_cntl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (bios_cntl & 1) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* BWE is RW, so the SMI was caused by a</span><br><span style="color: hsl(0, 100%, 40%);">- * write to BWE, not by a write to the BIOS</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* This is the place where we notice someone</span><br><span style="color: hsl(0, 100%, 40%);">- * is trying to tinker with the BIOS. We are</span><br><span style="color: hsl(0, 100%, 40%);">- * trying to be nice and just ignore it. A more</span><br><span style="color: hsl(0, 100%, 40%);">- * resolute answer would be to power down the</span><br><span style="color: hsl(0, 100%, 40%);">- * box.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));</span><br><span style="color: hsl(0, 100%, 40%);">- } /* No else for now? */</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (tco_sts & (1 << 3)) { /* TIMEOUT */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Handle TCO timeout */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO Timeout.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- dump_tco_status(tco_sts);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_periodic(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Are periodic SMIs enabled? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((reg32 & PERIODIC_EN) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Periodic SMI.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_monitor(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_smi_monitor(void)</span><br><span> {</span><br><span> #define IOTRAP(x) (trap_sts & (1 << x))</span><br><span> u32 trap_sts, trap_cycle;</span><br><span>@@ -782,76 +168,18 @@</span><br><span> #undef IOTRAP</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef void (*smi_handler_t)(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static smi_handler_t southbridge_smi[32] = {</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [0] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [1] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [2] BIOS_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [3] LEGACY_USB_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_sleep, // [4] SLP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_apmc, // [5] APM_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [6] SWSMI_TMR_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [7] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_pm1, // [8] PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_gpe0, // [9] GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_gpi, // [10] GPI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_mc, // [11] MCSMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [12] DEVMON_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_tco, // [13] TCO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_periodic, // [14] PERIODIC_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [15] SERIRQ_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [16] SMBUS_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [17] LEGACY_USB2_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [18] INTEL_USB2_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [19] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [20] PCI_EXP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_monitor, // [21] MONITOR_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [22] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [23] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [24] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [25] EL_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [26] SPI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [27] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [28] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [29] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [30] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL // [31] reserved</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Interrupt handler for SMI#</span><br><span style="color: hsl(0, 100%, 40%);">- * @param node</span><br><span style="color: hsl(0, 100%, 40%);">- * @param state_save</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smi_handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int i, dump = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smi_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Update global variable pmbase */</span><br><span style="color: hsl(0, 100%, 40%);">- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We need to clear the SMI status registers, or we won't see what's</span><br><span style="color: hsl(0, 100%, 40%);">- * happening in the following calls.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_sts = reset_smi_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call SMI sub handler for each of the status bits */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 31; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << i)) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (southbridge_smi[i]) {</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi[i]();</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "</span><br><span style="color: hsl(0, 100%, 40%);">- "handler available.\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- dump = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ em64t101_smm_state_save_area_t *state =</span><br><span style="color: hsl(120, 100%, 40%);">+ smi_apmc_find_state_save(apm_cnt);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (state) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EBX in the state save contains the GNVS pointer */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs = (global_nvs_t *)((u32)state->rbx);</span><br><span style="color: hsl(120, 100%, 40%);">+ *smm_done = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (dump) {</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smi_status(smi_sts);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_finalize_all(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26296">change 26296</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e </div>
<div style="display:none"> Gerrit-Change-Number: 26296 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>