<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26276">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/Intel/NativeRaminit: Style fixes<br><br>Fix tables and minor markdown bugs.<br><br>Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M Documentation/Intel/NativeRaminit/SandyBridge_registers.md<br>M Documentation/Intel/NativeRaminit/Sandybridge.md<br>M Documentation/Intel/NativeRaminit/Sandybridge_freq.md<br>M Documentation/Intel/NativeRaminit/Sandybridge_read.md<br>4 files changed, 1,474 insertions(+), 645 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/26276/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md</span><br><span>index bffbf76..601157c 100644</span><br><span>--- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md</span><br><span>+++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md</span><br><span>@@ -11,9 +11,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x10**</span><br><span> </span><br><span>@@ -21,12 +26,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x14**</span><br><span> </span><br><span>@@ -34,12 +46,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x18**</span><br><span> </span><br><span>@@ -47,12 +66,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x1c**</span><br><span> </span><br><span>@@ -60,12 +86,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x20**</span><br><span> </span><br><span>@@ -73,12 +106,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x24**</span><br><span> </span><br><span>@@ -86,12 +126,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x28**</span><br><span> </span><br><span>@@ -99,12 +146,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x2c**</span><br><span> </span><br><span>@@ -112,12 +166,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x204**</span><br><span> </span><br><span>@@ -125,9 +186,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x210**</span><br><span> </span><br><span>@@ -135,12 +201,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x214**</span><br><span> </span><br><span>@@ -148,12 +221,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x218**</span><br><span> </span><br><span>@@ -161,12 +241,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x21c**</span><br><span> </span><br><span>@@ -174,12 +261,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x220**</span><br><span> </span><br><span>@@ -187,12 +281,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x224**</span><br><span> </span><br><span>@@ -200,12 +301,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x228**</span><br><span> </span><br><span>@@ -213,12 +321,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x22c**</span><br><span> </span><br><span>@@ -226,12 +341,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x404**</span><br><span> </span><br><span>@@ -239,9 +361,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x410**</span><br><span> </span><br><span>@@ -249,12 +376,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x414**</span><br><span> </span><br><span>@@ -262,12 +396,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x418**</span><br><span> </span><br><span>@@ -275,12 +416,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x41c**</span><br><span> </span><br><span>@@ -288,12 +436,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x420**</span><br><span> </span><br><span>@@ -301,12 +456,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x424**</span><br><span> </span><br><span>@@ -314,12 +476,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x428**</span><br><span> </span><br><span>@@ -327,12 +496,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x42c**</span><br><span> </span><br><span>@@ -340,12 +516,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x604**</span><br><span> </span><br><span>@@ -353,9 +536,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x610**</span><br><span> </span><br><span>@@ -363,12 +551,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x614**</span><br><span> </span><br><span>@@ -376,12 +571,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x618**</span><br><span> </span><br><span>@@ -389,12 +591,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x61c**</span><br><span> </span><br><span>@@ -402,12 +611,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x620**</span><br><span> </span><br><span>@@ -415,12 +631,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x624**</span><br><span> </span><br><span>@@ -428,12 +651,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x628**</span><br><span> </span><br><span>@@ -441,12 +671,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x62c**</span><br><span> </span><br><span>@@ -454,12 +691,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x804**</span><br><span> </span><br><span>@@ -467,9 +711,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x810**</span><br><span> </span><br><span>@@ -477,12 +726,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x814**</span><br><span> </span><br><span>@@ -490,12 +746,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x818**</span><br><span> </span><br><span>@@ -503,12 +766,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x81c**</span><br><span> </span><br><span>@@ -516,12 +786,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x820**</span><br><span> </span><br><span>@@ -529,12 +806,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x824**</span><br><span> </span><br><span>@@ -542,12 +826,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x828**</span><br><span> </span><br><span>@@ -555,12 +846,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x82c**</span><br><span> </span><br><span>@@ -568,12 +866,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 4</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa04**</span><br><span> </span><br><span>@@ -581,9 +886,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa10**</span><br><span> </span><br><span>@@ -591,12 +901,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa14**</span><br><span> </span><br><span>@@ -604,12 +921,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa18**</span><br><span> </span><br><span>@@ -617,12 +941,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa1c**</span><br><span> </span><br><span>@@ -630,12 +961,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa20**</span><br><span> </span><br><span>@@ -643,12 +981,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa24**</span><br><span> </span><br><span>@@ -656,12 +1001,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa28**</span><br><span> </span><br><span>@@ -669,12 +1021,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xa2c**</span><br><span> </span><br><span>@@ -682,12 +1041,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc04**</span><br><span> </span><br><span>@@ -695,9 +1061,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc10**</span><br><span> </span><br><span>@@ -705,12 +1076,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc14**</span><br><span> </span><br><span>@@ -718,17 +1096,29 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| Rank 0 CLK phase shift, low |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| Rank 1 CLK phase shift, low |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:17| Rank 2 CLK phase shift, low |</span><br><span style="color: hsl(0, 100%, 40%);">-| 18:23| Rank 3 CLK phase shift, low |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:27| Rankmap to enable clock crossover on |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| Rank 0 CLK phase shift, low |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| Rank 1 CLK phase shift, low |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:17| Rank 2 CLK phase shift, low |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 18:23| Rank 3 CLK phase shift, low |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:27| Rankmap to enable clock crossover on |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc18**</span><br><span> </span><br><span>@@ -736,16 +1126,27 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 0 | Rank 0 CLK phase shift, high |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1 | Rank 1 CLK phase shift, high |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2 | Rank 2 CLK phase shift, high |</span><br><span style="color: hsl(0, 100%, 40%);">-| 3 | Rank 3 CLK phase shift, high |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | Rank 0 CLK phase shift, high |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | Rank 1 CLK phase shift, high |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | Rank 2 CLK phase shift, high |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 3 | Rank 3 CLK phase shift, high |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc1c**</span><br><span> </span><br><span>@@ -753,12 +1154,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc20**</span><br><span> </span><br><span>@@ -766,12 +1174,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc24**</span><br><span> </span><br><span>@@ -779,12 +1194,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc28**</span><br><span> </span><br><span>@@ -792,12 +1214,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xc2c**</span><br><span> </span><br><span>@@ -805,12 +1234,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 6</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe04**</span><br><span> </span><br><span>@@ -818,9 +1254,14 @@</span><br><span> </span><br><span> *Desc:* Lane training result Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:63| Training result, each bit corresponds to one of the 64 settings of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:63| Training result, each bit corresponds to one of the 64 settings |</span><br><span style="color: hsl(120, 100%, 40%);">+| | of IO delay |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe10**</span><br><span> </span><br><span>@@ -828,12 +1269,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe14**</span><br><span> </span><br><span>@@ -841,12 +1289,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe18**</span><br><span> </span><br><span>@@ -854,12 +1309,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe1c**</span><br><span> </span><br><span>@@ -867,12 +1329,19 @@</span><br><span> </span><br><span> *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 6:11| DQS phase shift on rising edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:18| IO delay in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:25| DQS phase shift on falling edge in 1/64 DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe20**</span><br><span> </span><br><span>@@ -880,12 +1349,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe24**</span><br><span> </span><br><span>@@ -893,12 +1369,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe28**</span><br><span> </span><br><span>@@ -906,12 +1389,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0xe2c**</span><br><span> </span><br><span>@@ -919,12 +1409,19 @@</span><br><span> </span><br><span> *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| DQ IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:13| DQS IO phase shift in 1/64th DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 15:17| DQS IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DQ IO phase shift in DCKs |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x1810**</span><br><span> </span><br><span>@@ -932,11 +1429,17 @@</span><br><span> </span><br><span> *Desc:* COMP1 Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 9:11| ODT |</span><br><span style="color: hsl(0, 100%, 40%);">-| 21:23| CLK drive up |</span><br><span style="color: hsl(0, 100%, 40%);">-| 27:29| CTRL drive up |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 9:11| ODT |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 21:23| CLK drive up |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 27:29| CTRL drive up |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x320c**</span><br><span> </span><br><span>@@ -944,13 +1447,21 @@</span><br><span> </span><br><span> *Desc:* Command crossover enable Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:5| CLK phase, low |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12 | CLK phase, high |</span><br><span style="color: hsl(0, 100%, 40%);">-| 14 | Enable hardware |</span><br><span style="color: hsl(0, 100%, 40%);">-| 17 | Enable on slot 1 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 27 | Enable on slot 2 |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:5| CLK phase, low |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12 | CLK phase, high |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 14 | Enable hardware |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 17 | Enable on slot 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 27 | Enable on slot 2 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x3714**</span><br><span> </span><br><span>@@ -958,9 +1469,13 @@</span><br><span> </span><br><span> *Desc:* COMP2 Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:31| COMP2 value |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:31| COMP2 value |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4000**</span><br><span> </span><br><span>@@ -968,13 +1483,21 @@</span><br><span> </span><br><span> *Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:3| tRCD |</span><br><span style="color: hsl(0, 100%, 40%);">-| 4:7| tRP |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:11| CAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:15| CWL |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:19| tRAS |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:3| tRCD |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 4:7| tRP |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:11| CAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:15| CWL |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:19| tRAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4004**</span><br><span> </span><br><span>@@ -982,16 +1505,32 @@</span><br><span> </span><br><span> *Desc:* TC_RAP - Timing of DDR - Regular Access Parameters Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:3| tRRD |</span><br><span style="color: hsl(0, 100%, 40%);">-| 4:7| tRTP |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:11| CKE |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:15| WTR |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:19| tFAW |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:27| tWR |</span><br><span style="color: hsl(0, 100%, 40%);">-| 29 | Command 3-state options, 0: Drive when channel is active, tri-state when inactive, 1: Always drive command bus |</span><br><span style="color: hsl(0, 100%, 40%);">-| 30:31| CMD stretch, 00: 1N, 10: 2N, 11: 3N |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:3| tRRD |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 4:7| tRTP |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:11| CKE |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:15| WTR |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:19| tFAW |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:27| tWR |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 29 | Command 3-state options |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0: Drive when channel is active, tri-state when inactive, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 1: Always drive command bus |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 30:31| CMD stretch, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 00b: 1N, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 10b: 2N, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 11b: 3N |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x400c**</span><br><span> </span><br><span>@@ -999,12 +1538,19 @@</span><br><span> </span><br><span> *Desc:* OTHP ODT control Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:3| tXPDLL ? |</span><br><span style="color: hsl(0, 100%, 40%);">-| 5:7| tXP ? |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:17| ODT stretch |</span><br><span style="color: hsl(0, 100%, 40%);">-| 18:19| ODT stretch |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:3| tXPDLL ? |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 5:7| tXP ? |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:17| ODT stretch |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 18:19| ODT stretch |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x401c**</span><br><span> </span><br><span>@@ -1012,10 +1558,15 @@</span><br><span> </span><br><span> *Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:13| ODT stretch |</span><br><span style="color: hsl(0, 100%, 40%);">-| 14:15| ODT stretch |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:13| ODT stretch |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 14:15| ODT stretch |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4024**</span><br><span> </span><br><span>@@ -1023,12 +1574,19 @@</span><br><span> </span><br><span> *Desc:* Rounttrip time Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:7| RTT Rank 0 DIMM 0 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:15| RTT Rank 1 DIMM 0 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:23| RTT Rank 0 DIMM 1 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:31| RTT Rank 1 DIMM 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:7| RTT Rank 0 DIMM 0 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:15| RTT Rank 1 DIMM 0 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:23| RTT Rank 0 DIMM 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:31| RTT Rank 1 DIMM 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4028**</span><br><span> </span><br><span>@@ -1036,13 +1594,21 @@</span><br><span> </span><br><span> *Desc:* SC_IO_LATENCY Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:3| IO latency Rank 0 DIMM 0 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 4:7| IO latency Rank 1 DIMM 0 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:11| IO latency Rank 0 DIMM 1 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:15| IO latency Rank 1 DIMM 1 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:21| Rount trip - I/O compensation |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:3| IO latency Rank 0 DIMM 0 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 4:7| IO latency Rank 1 DIMM 0 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:11| IO latency Rank 0 DIMM 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:15| IO latency Rank 1 DIMM 1 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:21| Rount trip - I/O compensation |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4200**</span><br><span> </span><br><span>@@ -1050,11 +1616,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, address Register, Channel 0, queue idx 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| Address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:22| Bank address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| Address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:22| Bank address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4204**</span><br><span> </span><br><span>@@ -1062,11 +1634,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, address Register, Channel 0, queue idx 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| Address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:22| Bank address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| Address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:22| Bank address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4208**</span><br><span> </span><br><span>@@ -1074,11 +1652,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, address Register, Channel 0, queue idx 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| Address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:22| Bank address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| Address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:22| Bank address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x420c**</span><br><span> </span><br><span>@@ -1086,11 +1670,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, address Register, Channel 0, queue idx 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| Address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20:22| Bank address |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| Address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20:22| Bank address |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:25| Slotrank |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4220**</span><br><span> </span><br><span>@@ -1098,11 +1688,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0 | !RAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1 | !CAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | !RAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | !CAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4224**</span><br><span> </span><br><span>@@ -1110,11 +1706,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0 | !RAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1 | !CAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | !RAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | !CAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4228**</span><br><span> </span><br><span>@@ -1122,11 +1724,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0 | !RAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1 | !CAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | !RAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | !CAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x422c**</span><br><span> </span><br><span>@@ -1134,11 +1742,17 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0 | !RAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1 | !CAS |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | !RAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | !CAS |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | !WE |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4230**</span><br><span> </span><br><span>@@ -1146,9 +1760,13 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4234**</span><br><span> </span><br><span>@@ -1156,9 +1774,13 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4238**</span><br><span> </span><br><span>@@ -1166,9 +1788,13 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 2</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x423c**</span><br><span> </span><br><span>@@ -1176,9 +1802,13 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:31| Clock cycles to wait after command |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4284**</span><br><span> </span><br><span>@@ -1186,10 +1816,15 @@</span><br><span> </span><br><span> *Desc:* RAM training queue, cooldown Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0 | Start executing DRAM command queue |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:19| (Number of queued commands - 1) * 4 |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0 | Start executing DRAM command queue |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:19| (Number of queued commands - 1) * 4 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4298**</span><br><span> </span><br><span>@@ -1197,11 +1832,19 @@</span><br><span> </span><br><span> *Desc:* TC - Refresh parameters Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| tREFI, average period between refresh in DCLK cycles |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:24| tRFC, Time of refresh, from beginning of refresh until next ACT or refresh is allowed in DCLK cycles |</span><br><span style="color: hsl(0, 100%, 40%);">-| 25:32| tREFIx9, Maximum time allowed between refreshes to a rank. Should be programmed to 8.9 * tREFI / 1024 |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| tREFI, average period between refresh in DCLK cycles |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:24| tRFC, Time of refresh, from beginning of refresh until next ACT |</span><br><span style="color: hsl(120, 100%, 40%);">+| | or refresh is allowed in DCLK cycles |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 25:32| tREFIx9, Maximum time allowed between refreshes to a rank. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | Should be programmed to 8.9 * tREFI / 1024 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x42a4**</span><br><span> </span><br><span>@@ -1209,12 +1852,19 @@</span><br><span> </span><br><span> *Desc:* SRFTP Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:11| tXSDLL |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:15| tXS_offset |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:25| tZQOPER |</span><br><span style="color: hsl(0, 100%, 40%);">-| 28:31| tMOD |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:11| tXSDLL |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:15| tXS_offset |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:25| tZQOPER |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 28:31| tMOD |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4c20**</span><br><span> </span><br><span>@@ -1222,9 +1872,13 @@</span><br><span> </span><br><span> *Desc:* Scheduler parameters Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:31| scheduler parameters |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:31| scheduler parameters |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4cb0**</span><br><span> </span><br><span>@@ -1232,10 +1886,26 @@</span><br><span> </span><br><span> *Desc:* PM - Power-down configuration, Broadcast Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:7| PDWN_idle_counter, This defines the rank indle period in DCLK cycles that causes power-down entrance. The minimum value should be greater then or equal to the worst roundtrip time plus burst length. |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:10| PDWN_mode, selects the mode of power-down: 0x0: No power down, 0x1: APD, 0x2: PPD, 0x3: APD+PPD, 0x4: Reserved, 0x5: Reserved, 0x6: PPD-DLLoff, 0x7: APD+PPD+DLLof |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:7| PDWN_idle_counter, This defines the rank indle period in DCLK |</span><br><span style="color: hsl(120, 100%, 40%);">+| | cycles that causes power-down entrance. The minimum value |</span><br><span style="color: hsl(120, 100%, 40%);">+| | should be greater then or equal to the worst roundtrip time |</span><br><span style="color: hsl(120, 100%, 40%);">+| | plus burst length. |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:10| PDWN_mode, selects the mode of power-down: |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x0: No power down, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x1: APD, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x2: PPD, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x3: APD+PPD, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x4: Reserved, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x5: Reserved, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x6: PPD-DLLoff, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0x7: APD+PPD+DLLof |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4e80**</span><br><span> </span><br><span>@@ -1243,9 +1913,13 @@</span><br><span> </span><br><span> *Desc:* Power mode preset Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:31| Power mode preset |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:31| Power mode preset |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4e94**</span><br><span> </span><br><span>@@ -1253,11 +1927,20 @@</span><br><span> </span><br><span> *Desc:* TC - Refresh parameters Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:7| OREF_RI, Rank idle period that defines an oppertunity for refresh |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:11| Refresh_HP_WM, tREFI count level that turns the refresh priority to high |</span><br><span style="color: hsl(0, 100%, 40%);">-| 12:15| Refresh_panic_WM, tREFI count level in which the refresh priority is panic |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:7| OREF_RI, Rank idle period that defines an oppertunity for |</span><br><span style="color: hsl(120, 100%, 40%);">+| | refresh |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:11| Refresh_HP_WM, tREFI count level that turns the refresh |</span><br><span style="color: hsl(120, 100%, 40%);">+| | priority to high |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 12:15| Refresh_panic_WM, tREFI count level in which the refresh |</span><br><span style="color: hsl(120, 100%, 40%);">+| | priority is panic |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x4e98**</span><br><span> </span><br><span>@@ -1265,11 +1948,19 @@</span><br><span> </span><br><span> *Desc:* TC - Refresh parameters Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| tREFI, average period between refresh in DCLK cycles |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16:24| tRFC, Time of refresh, from beginning of refresh until next ACT or refresh is allowed in DCLK cycles |</span><br><span style="color: hsl(0, 100%, 40%);">-| 25:32| tREFIx9, Maximum time allowed between refreshes to a rank. Should be programmed to 8.9 * tREFI / 1024 |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| tREFI, average period between refresh in DCLK cycles |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16:24| tRFC, Time of refresh, from beginning of refresh until next ACT |</span><br><span style="color: hsl(120, 100%, 40%);">+| | or refresh is allowed in DCLK cycles |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 25:32| tREFIx9, Maximum time allowed between refreshes to a rank. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | Should be programmed to 8.9 * tREFI / 1024 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5000**</span><br><span> </span><br><span>@@ -1277,11 +1968,26 @@</span><br><span> </span><br><span> *Desc:* Global channel size control Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:1| CH_A, defines the largest channel. 00: Channel 0, 01: Channel 1, 10: Channel 2 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2:3| CH_B, defines the mid-size channel. 00: Channel 0, 01: Channel 1, 10: Channel 2 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2:3| CH_C, defines the smallest channel. 00: Channel 0, 01: Channel 1, 10: Channel 2, CH_C is 10 if only 2 channels are supported |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:1| CH_A, defines the largest channel. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 00b: Channel 0, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 01b: Channel 1, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 10b: Channel 2 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2:3| CH_B, defines the mid-size channel. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 00b: Channel 0, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 01b: Channel 1, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 10b: Channel 2 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2:3| CH_C, defines the smallest channel. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 00b: Channel 0, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 01b: Channel 1, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 10b: Channel 2, CH_C is 10 if only 2 channels are supported |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5004**</span><br><span> </span><br><span>@@ -1289,20 +1995,41 @@</span><br><span> </span><br><span> *Desc:* Address Decode Register, Channel 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:7| DIMMA size in 256 MB multiples |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16 | DIMM A select (DAS) Slot to DIMM mapping, 0: DIMMA, DIMMB, 1: DIMMB, DIMMA |</span><br><span style="color: hsl(0, 100%, 40%);">-| 17 | DIMM A number of ranks |</span><br><span style="color: hsl(0, 100%, 40%);">-| 19 | DIMM A DRAM width x8 / x16 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8:15| DIMM B size in 256 MB multiples |</span><br><span style="color: hsl(0, 100%, 40%);">-| 18 | DIMM B number of ranks |</span><br><span style="color: hsl(0, 100%, 40%);">-| 20 | DIMM B DRAM width in 8x / x16 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 21 | Rank interleave enable |</span><br><span style="color: hsl(0, 100%, 40%);">-| 22 | Enhanced interleave enable |</span><br><span style="color: hsl(0, 100%, 40%);">-| 26 | High order Rank interleave enable |</span><br><span style="color: hsl(0, 100%, 40%);">-| 27:29| High Order Rank interleave Address. Selects on of address bits 20-27 to use for high rank interleave |</span><br><span style="color: hsl(0, 100%, 40%);">-| 24:25| ECC, 00: No ECC active, 01: ECC is active on IO, 11: ECC is active on both IO and ECC logic |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:7| DIMMA size in 256 MB multiples |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16 | DIMM A select (DAS) Slot to DIMM mapping, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0: DIMMA, DIMMB, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 1: DIMMB, DIMMA |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 17 | DIMM A number of ranks |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 19 | DIMM A DRAM width x8 / x16 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8:15| DIMM B size in 256 MB multiples |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 18 | DIMM B number of ranks |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 20 | DIMM B DRAM width in 8x / x16 |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 21 | Rank interleave enable |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 22 | Enhanced interleave enable |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 26 | High order Rank interleave enable |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 27:29| High Order Rank interleave Address. Selects on of address bits |</span><br><span style="color: hsl(120, 100%, 40%);">+| | 20-27 to use for high rank interleave |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 24:25| ECC, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 00b: No ECC active, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 01b: ECC is active on IO, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 11b: ECC is active on both IO and ECC logic |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5030**</span><br><span> </span><br><span>@@ -1310,11 +2037,17 @@</span><br><span> </span><br><span> *Desc:* Global DDR3 control Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 1 | DDR reset |</span><br><span style="color: hsl(0, 100%, 40%);">-| 2 | DCLK enable |</span><br><span style="color: hsl(0, 100%, 40%);">-| 5 | IO reset |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1 | DDR reset |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 2 | DCLK enable |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 5 | IO reset |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5034**</span><br><span> </span><br><span>@@ -1322,9 +2055,13 @@</span><br><span> </span><br><span> *Desc:* Version Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:31| MRC version |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:31| MRC version |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5060**</span><br><span> </span><br><span>@@ -1332,10 +2069,18 @@</span><br><span> </span><br><span> *Desc:* PM - Self refresh config Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:15| Idle_timer, The value is used when the SREF_enable field is set and defines the # of cycles that there should not be any transaction in order to enter self-refresh. |</span><br><span style="color: hsl(0, 100%, 40%);">-| 16 | SR_Enable, enable self-refresh mechanism. Clear SREF_en and SREF_exit first. |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:15| Idle_timer, The value is used when the SREF_enable field is set |</span><br><span style="color: hsl(120, 100%, 40%);">+| | and defines the # of cycles that there should not be any |</span><br><span style="color: hsl(120, 100%, 40%);">+| | transaction in order to enter self-refresh. |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16 | SR_Enable, enable self-refresh mechanism. Clear SREF_en and |</span><br><span style="color: hsl(120, 100%, 40%);">+| | SREF_exit first. |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5084**</span><br><span> </span><br><span>@@ -1343,9 +2088,13 @@</span><br><span> </span><br><span> *Desc:* RCOMP status Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 16 | Busy |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 16 | Busy |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5090**</span><br><span> </span><br><span>@@ -1353,9 +2102,13 @@</span><br><span> </span><br><span> *Desc:* ECC - Address compare for ECC error injection Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:31| Inject error when ECC_Inj_Addr_Compare[31:0] = ADDR[37:6] |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:31| Inject error when ECC_Inj_Addr_Compare[31:0] = ADDR[37:6] |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5094**</span><br><span> </span><br><span>@@ -1363,9 +2116,14 @@</span><br><span> </span><br><span> *Desc:* ECC - Address mask for ECC error injection Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = |</span><br><span style="color: hsl(120, 100%, 40%);">+| | ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5e00**</span><br><span> </span><br><span>@@ -1373,11 +2131,18 @@</span><br><span> </span><br><span> *Desc:* MC_BIOS_REQ Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |</span><br><span style="color: hsl(0, 100%, 40%);">-| 8 | 1: 100Mhz reference clock, 0: 133Mhz reference clock (IvyBridge only) |</span><br><span style="color: hsl(0, 100%, 40%);">-| 31 | PLL busy |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8 | - 1: 100Mhz reference clock |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0: 133Mhz reference clock (IvyBridge only) |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 31 | PLL busy |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5e04**</span><br><span> </span><br><span>@@ -1385,9 +2150,15 @@</span><br><span> </span><br><span> *Desc:* MC_BIOS_DATA Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 0:7| Active multiplier: 100Mhz [7,12], 133Mhz [3,19] |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 0:7| Active multiplier: |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 100Mhz [7,12], |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 133Mhz [3,19] |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> **MCHBAR + 0x5f08**</span><br><span> </span><br><span>@@ -1395,6 +2166,9 @@</span><br><span> </span><br><span> *Desc:* RCOMP control Register</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-|Bit| Description |</span><br><span style="color: hsl(0, 100%, 40%);">-|---|-------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| 8 | Force RCOMP |</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Bit | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========+==================================================================+</span><br><span style="color: hsl(120, 100%, 40%);">+| 8 | Force RCOMP |</span><br><span style="color: hsl(120, 100%, 40%);">++-----------+------------------------------------------------------------------+</span><br><span>diff --git a/Documentation/Intel/NativeRaminit/Sandybridge.md b/Documentation/Intel/NativeRaminit/Sandybridge.md</span><br><span>index 8203106..5c83a0d 100644</span><br><span>--- a/Documentation/Intel/NativeRaminit/Sandybridge.md</span><br><span>+++ b/Documentation/Intel/NativeRaminit/Sandybridge.md</span><br><span>@@ -18,16 +18,27 @@</span><br><span> * Error handling</span><br><span> </span><br><span> ## Definitions</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span> | Symbol | Description | Units | Valid region |</span><br><span style="color: hsl(0, 100%, 40%);">-|---------|-------------------------------------------------------------------|------------|--------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| SCK | DRAM system clock cycle time | s | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| tCK | DRAM system clock cycle time | 1/256th ns | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |</span><br><span style="color: hsl(120, 100%, 40%);">++=========+===================================================================+============+==============+</span><br><span style="color: hsl(120, 100%, 40%);">+| SCK | DRAM system clock cycle time | s | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| tCK | DRAM system clock cycle time | 1/256th ns | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DCK | Data clock cycle time: The time between two SCK clock edges | s | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span> | timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |</span><br><span style="color: hsl(0, 100%, 40%);">-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span> | REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |</span><br><span style="color: hsl(0, 100%, 40%);">-| MULT | DRAM PLL multiplier | - | [3-12] |</span><br><span style="color: hsl(0, 100%, 40%);">-| XMP | Extreme Memory Profiles | - | - |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| MULT | DRAM PLL multiplier | | [3-12] |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| XMP | Extreme Memory Profiles | | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> ## (Inoffical) register documentation</span><br><span> - [Sandy Bride - Register documentation](SandyBridge_registers.md)</span><br><span>diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md</span><br><span>index 50c6362..cf68d5e 100644</span><br><span>--- a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md</span><br><span>+++ b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md</span><br><span>@@ -4,16 +4,25 @@</span><br><span> This chapter explains the frequency selection done on Sandybride and Ivybridge.</span><br><span> </span><br><span> ## Definitions</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span> | Symbol | Description | Units | Valid region |</span><br><span style="color: hsl(0, 100%, 40%);">-|---------|-------------------------------------------------------------------|------------|--------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| SCK | DRAM system clock cycle time | s | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| tCK | DRAM system clock cycle time | 1/256th ns | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |</span><br><span style="color: hsl(0, 100%, 40%);">-| MULT | DRAM PLL multiplier | - | [3-12] |</span><br><span style="color: hsl(0, 100%, 40%);">-| XMP | Extreme Memory Profiles | - | - |</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">++=========+===================================================================+============+==============+</span><br><span style="color: hsl(120, 100%, 40%);">+| SCK | DRAM system clock cycle time | s | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| tCK | DRAM system clock cycle time | 1/256th ns | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DCK | Data clock cycle time: The time between two SCK clock edges | s | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| MULT | DRAM PLL multiplier | | [3-12] |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| XMP | Extreme Memory Profiles | | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> ## SPD</span><br><span> The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")</span><br><span> located on every DIMM is factory program with various timings. One of them</span><br><span>@@ -84,31 +93,54 @@</span><br><span> > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.</span><br><span> </span><br><span> ## Sandy Bride's supported frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |</span><br><span style="color: hsl(0, 100%, 40%);">-|------------|-----------|------------------|-------------------------|---------------|</span><br><span style="color: hsl(120, 100%, 40%);">++============+===========+==================+=========================+===============+</span><br><span> | 400 | DDR3-800 | 3 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 533 | DDR3-1066 | 4 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 666 | DDR3-1333 | 5 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 800 | DDR3-1600 | 6 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 933 | DDR3-1866 | 7 | 133 MHz | |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1066 | DDR3-2166 | 8 | 133 MHz | ||</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1066 | DDR3-2166 | 8 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> ## Ivybridge's supported frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |</span><br><span style="color: hsl(0, 100%, 40%);">-|------------|-----------|------------------|-------------------------|---------------|</span><br><span style="color: hsl(120, 100%, 40%);">++============+===========+==================+=========================+===============+</span><br><span> | 400 | DDR3-800 | 3 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 533 | DDR3-1066 | 4 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 666 | DDR3-1333 | 5 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 800 | DDR3-1600 | 6 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 933 | DDR3-1866 | 7 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 1066 | DDR3-2166 | 8 | 133 MHz | |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 700 | DDR3-1400 | 7 | 100 MHz | '1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 800 | DDR3-1600 | 8 | 100 MHz | '1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 900 | DDR3-1800 | 9 | 100 MHz | '1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 1000 | DDR3-2000 | 10 | 100 MHz | '1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span> | 1100 | DDR3-2200 | 11 | 100 MHz | '1 |</span><br><span style="color: hsl(0, 100%, 40%);">-| 1200 | DDR3-2400 | 12 | 100 MHz | '1 ||</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| 1200 | DDR3-2400 | 12 | 100 MHz | '1 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------+-----------+------------------+-------------------------+---------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> > '1: since coreboot 4.6</span><br><span> </span><br><span> ## Multiplier selection</span><br><span>@@ -120,7 +152,8 @@</span><br><span> freq_max := soft_fuse_max_mhz</span><br><span> </span><br><span> for i in SPDs:</span><br><span style="color: hsl(0, 100%, 40%);">- freq_max := MIN(freq_max, ddr_spd_max_mhz[i])```</span><br><span style="color: hsl(120, 100%, 40%);">+ freq_max := MIN(freq_max, ddr_spd_max_mhz[i])</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> </span><br><span> As you can see, by using DIMMs with different maximum DRAM frequencies, the</span><br><span> slowest DIMMs' frequency will be selected, to prevent over-clocking it.</span><br><span>diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_read.md b/Documentation/Intel/NativeRaminit/Sandybridge_read.md</span><br><span>index 5a5aa18..e58298a 100644</span><br><span>--- a/Documentation/Intel/NativeRaminit/Sandybridge_read.md</span><br><span>+++ b/Documentation/Intel/NativeRaminit/Sandybridge_read.md</span><br><span>@@ -23,18 +23,29 @@</span><br><span> The values programmed in read training effect DRAM-to-MC transfers only !</span><br><span> </span><br><span> ## Definitions</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span> | Symbol | Description | Units | Valid region |</span><br><span style="color: hsl(0, 100%, 40%);">-|---------|-------------------------------------------------------------------|------------|--------------|</span><br><span style="color: hsl(0, 100%, 40%);">-| SCK | DRAM system clock cycle time | s | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| tCK | DRAM system clock cycle time | 1/256th ns | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |</span><br><span style="color: hsl(120, 100%, 40%);">++=========+===================================================================+============+==============+</span><br><span style="color: hsl(120, 100%, 40%);">+| SCK | DRAM system clock cycle time | s | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| tCK | DRAM system clock cycle time | 1/256th ns | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DCK | Data clock cycle time: The time between two SCK clock edges | s | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span> | timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |</span><br><span style="color: hsl(0, 100%, 40%);">-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |</span><br><span style="color: hsl(0, 100%, 40%);">-| MULT | DRAM PLL multiplier | - | [3-12] |</span><br><span style="color: hsl(0, 100%, 40%);">-| XMP | Extreme Memory Profiles | - | - |</span><br><span style="color: hsl(0, 100%, 40%);">-| DQS | Data Strobe signal used to sample all lane's DQ signals | - | - |</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| MULT | DRAM PLL multiplier | | [3-12] |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| XMP | Extreme Memory Profiles | | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DQS | Data Strobe signal used to sample all lane's DQ signals | | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------+-------------------------------------------------------------------+------------+--------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span> ## Hardware</span><br><span> The hardware does have delay logic blocks that can delay the DQ / DQS of a</span><br><span> lane/rank by one or multiple clock cylces and it does have delay logic blocks</span><br><span>@@ -66,18 +77,18 @@</span><br><span> The highest IO delay was set on the right-hand side, while the last block</span><br><span> on the left-hand side has zero IO delay.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-** roundtrip 55 DCKs **</span><br><span style="color: hsl(120, 100%, 40%);">+#### roundtrip 55 DCKs</span><br><span> ![alt text][timA_lane0-3_rt55]</span><br><span> </span><br><span> [timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-** roundtrip 54 DCKs **</span><br><span style="color: hsl(120, 100%, 40%);">+#### roundtrip 54 DCKs</span><br><span> ![alt text][timA_lane0-3_rt54]</span><br><span> </span><br><span> [timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-** roundtrip 53 DCKs **</span><br><span style="color: hsl(120, 100%, 40%);">+#### roundtrip 53 DCKs</span><br><span> ![alt text][timA_lane0-3_rt53]</span><br><span> </span><br><span> [timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26276">change 26276</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd </div>
<div style="display:none"> Gerrit-Change-Number: 26276 </div>
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<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>