<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26246">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I2cc18ceab33fc47302cc440dc1b6d9e2329401f2<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/common/acpi_pirq_gen.c<br>M src/southbridge/intel/common/acpi_pirq_gen.h<br>M src/southbridge/intel/common/rcba_pirq.c<br>M src/southbridge/intel/common/spi.c<br>4 files changed, 6 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/26246/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c</span><br><span>index fc26d1a..dbd2bc0 100644</span><br><span>--- a/src/southbridge/intel/common/acpi_pirq_gen.c</span><br><span>+++ b/src/southbridge/intel/common/acpi_pirq_gen.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span> const char *lpcb_path)</span><br><span> {</span><br><span> char buffer[DEVICE_PATH_MAX];</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> pci_pin_t prev_int_pin = PCI_INT_NONE;</span><br><span> u8 prev_pci_dev = 0;</span><br><span> size_t num_devs = 0;</span><br><span>@@ -88,7 +88,7 @@</span><br><span> return num_devs;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void intel_acpi_gen_def_acpi_pirq(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_acpi_gen_def_acpi_pirq(struct device *dev)</span><br><span> {</span><br><span> const char *lpcb_path = acpi_device_path(dev);</span><br><span> const size_t num_devs = enumerate_root_pci_pins(EMIT_NONE, lpcb_path);</span><br><span>diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h</span><br><span>index bd702da..c01fcd8 100644</span><br><span>--- a/src/southbridge/intel/common/acpi_pirq_gen.h</span><br><span>+++ b/src/southbridge/intel/common/acpi_pirq_gen.h</span><br><span>@@ -36,7 +36,7 @@</span><br><span> PIRQ_H,</span><br><span> } pirq_t;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void intel_acpi_gen_def_acpi_pirq(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin);</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_acpi_gen_def_acpi_pirq(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+enum pirq intel_common_map_pirq(const struct device *dev, const pci_pin_t pci_pin);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c</span><br><span>index 44d2f3d..d298951 100644</span><br><span>--- a/src/southbridge/intel/common/rcba_pirq.c</span><br><span>+++ b/src/southbridge/intel/common/rcba_pirq.c</span><br><span>@@ -12,7 +12,7 @@</span><br><span> D26IR, D27IR, D28IR, D29IR, D30IR, D31IR,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin)</span><br><span style="color: hsl(120, 100%, 40%);">+enum pirq intel_common_map_pirq(const struct device *dev, const pci_pin_t pci_pin)</span><br><span> {</span><br><span> u8 slot = PCI_SLOT(dev->path.pci.devfn);</span><br><span> u8 shift = 4 * (pci_pin - PCI_INT_A);</span><br><span>diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c</span><br><span>index 8cb5e62..4d75fa2 100644</span><br><span>--- a/src/southbridge/intel/common/spi.c</span><br><span>+++ b/src/southbridge/intel/common/spi.c</span><br><span>@@ -292,7 +292,7 @@</span><br><span> uint8_t *rcrb; /* Root Complex Register Block */</span><br><span> uint32_t rcba; /* Root Complex Base Address */</span><br><span> uint8_t bios_cntl;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> ich9_spi_regs *ich9_spi;</span><br><span> ich7_spi_regs *ich7_spi;</span><br><span> uint16_t hsfs;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26246">change 26246</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2cc18ceab33fc47302cc440dc1b6d9e2329401f2 </div>
<div style="display:none"> Gerrit-Change-Number: 26246 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>