<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26253">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801bx: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I661b2435d9f0306b246a3e89aac24eb30c959085<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/i82801bx/i82801bx.c<br>M src/southbridge/intel/i82801bx/i82801bx.h<br>M src/southbridge/intel/i82801bx/lpc.c<br>M src/southbridge/intel/i82801bx/smbus.c<br>M src/southbridge/intel/i82801bx/watchdog.c<br>5 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/26253/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/i82801bx/i82801bx.c b/src/southbridge/intel/i82801bx/i82801bx.c</span><br><span>index 99d630f..163b6f4 100644</span><br><span>--- a/src/southbridge/intel/i82801bx/i82801bx.c</span><br><span>+++ b/src/southbridge/intel/i82801bx/i82801bx.c</span><br><span>@@ -21,10 +21,10 @@</span><br><span> #include <device/pci.h></span><br><span> #include "i82801bx.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void i82801bx_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void i82801bx_enable(struct device *dev)</span><br><span> {</span><br><span> u16 reg16, index;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t lpc_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *lpc_dev;</span><br><span> </span><br><span> /* Search for the 82801BA/BAM LPC device (D31:F0) on PCI bus 0. */</span><br><span> lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span>diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h</span><br><span>index 3ecfe72..7a64979 100644</span><br><span>--- a/src/southbridge/intel/i82801bx/i82801bx.h</span><br><span>+++ b/src/southbridge/intel/i82801bx/i82801bx.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> </span><br><span> #if !defined(__PRE_RAM__)</span><br><span> #include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-extern void i82801bx_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+extern void i82801bx_enable(struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> #if defined(__PRE_RAM__)</span><br><span>diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c</span><br><span>index 0d8ebe0..4fbc004 100644</span><br><span>--- a/src/southbridge/intel/i82801bx/lpc.c</span><br><span>+++ b/src/southbridge/intel/i82801bx/lpc.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> /* TODO: Explain/#define the real meaning of these magic numbers. */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model)</span><br><span> {</span><br><span> u8 reg8;</span><br><span> config_t *config = dev->chip_info;</span><br><span>@@ -150,7 +150,7 @@</span><br><span> pci_write_config8(dev, PIRQH_ROUT, reg8);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801bx_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801bx_power_options(struct device *dev)</span><br><span> {</span><br><span> uint8_t byte;</span><br><span> int pwr_on = -1;</span><br><span>@@ -180,7 +180,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gpio_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gpio_init(struct device *dev)</span><br><span> {</span><br><span> /* Set the value for GPIO base address register and enable GPIO. */</span><br><span> pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));</span><br><span>@@ -222,7 +222,7 @@</span><br><span> pci_write_config16(dev, PCI_DMA_CFG, reg16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model)</span><br><span> {</span><br><span> /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.</span><br><span> * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.</span><br><span>@@ -269,7 +269,7 @@</span><br><span> i82801bx_lpc_decode_en(dev, ich_model);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801bx_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801bx_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c</span><br><span>index 01e8c37..90975cd 100644</span><br><span>--- a/src/southbridge/intel/i82801bx/smbus.c</span><br><span>+++ b/src/southbridge/intel/i82801bx/smbus.c</span><br><span>@@ -22,7 +22,7 @@</span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "i82801bx.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span> u16 device;</span><br><span> struct resource *res;</span><br><span>diff --git a/src/southbridge/intel/i82801bx/watchdog.c b/src/southbridge/intel/i82801bx/watchdog.c</span><br><span>index 60a7b57..d0af76c 100644</span><br><span>--- a/src/southbridge/intel/i82801bx/watchdog.c</span><br><span>+++ b/src/southbridge/intel/i82801bx/watchdog.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> unsigned long value, base;</span><br><span> </span><br><span> /* Turn off the ICH5 watchdog. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26253">change 26253</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I661b2435d9f0306b246a3e89aac24eb30c959085 </div>
<div style="display:none"> Gerrit-Change-Number: 26253 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>