<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26248">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/fsp_bd82x6x: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I499414c067b06fa94b53832894e804118f7c3e80<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/fsp_bd82x6x/azalia.c<br>M src/southbridge/intel/fsp_bd82x6x/lpc.c<br>M src/southbridge/intel/fsp_bd82x6x/me.c<br>M src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>M src/southbridge/intel/fsp_bd82x6x/pch.c<br>M src/southbridge/intel/fsp_bd82x6x/pch.h<br>M src/southbridge/intel/fsp_bd82x6x/sata.c<br>M src/southbridge/intel/fsp_bd82x6x/smihandler.c<br>M src/southbridge/intel/fsp_bd82x6x/watchdog.c<br>9 files changed, 35 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26248/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c</span><br><span>index b8cdd97..818c6f7 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/azalia.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c</span><br><span>@@ -334,7 +334,7 @@</span><br><span>      pci_write_config8(dev, 0x43, reg8);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c</span><br><span>index f17a44f..431587d 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c</span><br><span>@@ -112,9 +112,9 @@</span><br><span>  * 0x80 - The PIRQ is not routed.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *irq_dev;</span><br><span>      /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span> </span><br><span>@@ -154,7 +154,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_gpi_routing(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_gpi_routing(struct device *dev)</span><br><span> {</span><br><span>    /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -183,7 +183,7 @@</span><br><span>  pci_write_config32(dev, GPIO_ROUT, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span> {</span><br><span>       u8 reg8;</span><br><span>     u16 reg16, pmbase;</span><br><span>@@ -503,7 +503,7 @@</span><br><span>     pch_fixups(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>       struct resource *res;</span><br><span>        config_t *config = dev->chip_info;</span><br><span>@@ -564,18 +564,18 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span>  pch_decode_init(dev);</span><br><span>        return pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable(struct device *dev)</span><br><span> {</span><br><span>  pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -586,7 +586,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span>    global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));</span><br><span> </span><br><span>@@ -612,7 +612,7 @@</span><br><span> </span><br><span> void acpi_fill_fadt(acpi_fadt_t *fadt)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span>    config_t *chip = dev->chip_info;</span><br><span>  u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;</span><br><span>      int c2_latency;</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c</span><br><span>index a4b5f03..f3a7824 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/me.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/me.c</span><br><span>@@ -114,7 +114,7 @@</span><br><span> }</span><br><span> </span><br><span> #ifndef __SMM__</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span>      u32 dword = pci_read_config32(dev, offset);</span><br><span>  memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -542,7 +542,7 @@</span><br><span> #else /* !__SMM__ */</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span>      me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span>    struct me_hfs hfs;</span><br><span>@@ -609,7 +609,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res;</span><br><span>        struct mei_csr host;</span><br><span>@@ -639,7 +639,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span>   struct me_heres status;</span><br><span>      u32 extend[8] = {0};</span><br><span>@@ -686,14 +686,14 @@</span><br><span> }</span><br><span> </span><br><span> /* Hide the ME virtual PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_hide(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_hide(struct device *dev)</span><br><span> {</span><br><span>    dev->enabled = 0;</span><br><span>         pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span>  me_bios_path path = intel_me_path(dev);</span><br><span> </span><br><span>@@ -735,7 +735,7 @@</span><br><span>    }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c</span><br><span>index fd8b167..03a9d45 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c</span><br><span>@@ -115,7 +115,7 @@</span><br><span> }</span><br><span> </span><br><span> #ifndef __SMM__</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span>     u32 dword = pci_read_config32(dev, offset);</span><br><span>  memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -521,7 +521,7 @@</span><br><span> #else /* !__SMM__ */</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span>      me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span>    struct me_hfs hfs;</span><br><span>@@ -595,7 +595,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res;</span><br><span>        struct mei_csr host;</span><br><span>@@ -625,7 +625,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span>   struct me_heres status;</span><br><span>      u32 extend[8] = {0};</span><br><span>@@ -672,14 +672,14 @@</span><br><span> }</span><br><span> </span><br><span> /* Hide the ME virtual PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_hide(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_hide(struct device *dev)</span><br><span> {</span><br><span>    dev->enabled = 0;</span><br><span>         pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span>  me_bios_path path = intel_me_path(dev);</span><br><span>      me_bios_payload mbp_data;</span><br><span>@@ -737,7 +737,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.c b/src/southbridge/intel/fsp_bd82x6x/pch.c</span><br><span>index 3ad45fc..1613be8 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/pch.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/pch.c</span><br><span>@@ -188,9 +188,9 @@</span><br><span> }</span><br><span> </span><br><span> /* Check if any port in set X to X+3 is enabled */</span><br><span style="color: hsl(0, 100%, 40%);">-static int pch_pcie_check_set_enabled(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int pch_pcie_check_set_enabled(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t port;</span><br><span style="color: hsl(120, 100%, 40%);">+        struct device *port;</span><br><span>         int port_func;</span><br><span>       int dev_func = PCI_FUNC(dev->path.pci.devfn);</span><br><span> </span><br><span>@@ -237,7 +237,7 @@</span><br><span> /* Update devicetree with new Root Port function number assignment */</span><br><span> static void pch_pcie_devicetree_update(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> </span><br><span>      /* Update the function numbers in the static devicetree */</span><br><span>   for (dev = all_devices; dev; dev = dev->next) {</span><br><span>@@ -266,7 +266,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Special handling for PCIe Root Port devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(struct device *dev)</span><br><span> {</span><br><span>        struct southbridge_intel_fsp_bd82x6x_config *config = dev->chip_info;</span><br><span>     u32 reg32;</span><br><span>@@ -373,7 +373,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev)</span><br><span> {</span><br><span>    u32 reg32;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>index 84f21a7..5b42271 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>@@ -65,7 +65,7 @@</span><br><span> int pch_silicon_revision(void);</span><br><span> int pch_silicon_type(void);</span><br><span> int pch_silicon_supported(int type, int rev);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev);</span><br><span> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);</span><br><span> #if IS_ENABLED(CONFIG_ELOG)</span><br><span> void pch_log_state(void);</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c</span><br><span>index 6130646..368a1b3 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/sata.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/sata.c</span><br><span>@@ -78,11 +78,11 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c</span><br><span>index 83eab79..213a44a 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c</span><br><span>@@ -242,7 +242,7 @@</span><br><span>  for (slot = 0; slot < 0x20; slot++) {</span><br><span>             for (func = 0; func < 8; func++) {</span><br><span>                        u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-                      device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+                      struct device *dev = PCI_DEV(bus, slot, func);</span><br><span> </span><br><span>                   val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/watchdog.c b/src/southbridge/intel/fsp_bd82x6x/watchdog.c</span><br><span>index 74f69b0..9a867e4 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/watchdog.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/watchdog.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span>   //</span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  unsigned long value, base;</span><br><span> </span><br><span>       /* Turn off the ICH7 watchdog. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26248">change 26248</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26248"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I499414c067b06fa94b53832894e804118f7c3e80 </div>
<div style="display:none"> Gerrit-Change-Number: 26248 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>